Recent activity in Combinational Circuits / GO Electronics

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GATE ECE 2010 | Question: 12
For the output $\text{F}$ to be $1$ in the logic circuit shown, the input combination should be $\mathrm{A}=1, \mathrm{~B}=1, \mathrm{C}=0$ $\text{A = 1, B = 0, C = 0}$ $\mathrm{A}=0, \mathrm{~B}=1, \mathrm{C}=0$ $\text{A = 0, B = 0, C = 1}$

For the output $\text{F}$ to be $1$ in the logic circuit shown, the input combination should be$\mathrm{A}=1, \mathrm{~B}=1, \mathrm{C}=0$$\text{A = 1, B = 0, C = 0}$$\ma...

Deepak Poonia

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Deepak Poonia answer edited Oct 17, 2023

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GATE ECE 2010 | Question: 11
Match the logic gates in Column A with their equivalents in Column B. $\text{P-2, Q-4, R-1, S-3}$ $\text{P-4, Q-2, R-1, S-3}$ $\text{P-2, Q-4, R-3, S-1}$ $\text{P-4, Q-2, R-3, S-1}$

Match the logic gates in Column A with their equivalents in Column B.$\text{P-2, Q-4, R-1, S-3}$$\text{P-4, Q-2, R-1, S-3}$$\text{P-2, Q-4, R-3, S-1}$$\text{P-4, Q-2, R-3...

Deepak Poonia

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Deepak Poonia answer edited Oct 10, 2023

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GATE ECE 2014 Set 2 | Question: 41
The outputs of the two flip-flops $Q1$, $Q2$ in the figure shown are initialized to $0,0$. The sequence generated at $Q1$ upon application of clock signal is $01110 \dots$ $01010\dots$ $00110\dots$ $01100\dots$

The outputs of the two flip-flops $Q1$, $Q2$ in the figure shown are initialized to $0,0$. The sequence generated at $Q1$ upon application of clock signal is $01110 \dots...

gatecse

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gatecse recategorized Nov 21, 2022

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GATE ECE 2014 Set 1 | Question: 40
The output $F$ in the digital logic circuit shown in the figure is $F = \overline{X}\:Y\:Z + X\:\overline{Y}\:Z$ $F = \overline{X}\:Y\:\overline{Z} + X\:\overline{Y}\:\overline{Z}$ $F = \overline{X}\:\overline{Y}\:Z + X\:Y\:Z$ $F = \overline{X}\:\overline{Y}\:\overline{Z} + X\:Y\:Z$

The output $F$ in the digital logic circuit shown in the figure is$F = \overline{X}\:Y\:Z + X\:\overline{Y}\:Z$$F = \overline{X}\:Y\:\overline{Z} + X\:\overline{Y}\:\over...

gatecse

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gatecse edited Sep 13, 2022