Recent questions tagged flip-flops

A binary ripple counter is designed to count $(0)_{10}$ to $(64)_{10}$.Which of the following is/are the number of flip-flops required to design the counter?$6$$7$$4$$5$

The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a square wave of $10$ cycles/second is applied to its clock (C) input.The...

In a $\text{J-K}$ flip-flip we have $\text{J} = \overline{Q}$ and $\text{K}=1$. Assuming the flip-flop was initially cleared and then clocked for $6$ puleses, the sequenc...

In the modulo-$6$ ripple counter shown in the given figure, the output of the $2$-input gate is used to clear the J-K flip-flops.The $2$-input gate isa NAND gatea NOR gat...

The given figure shows a ripple counter using positive edge triggered flip-flops. If the present state of the counter is $Q_{2}Q_{1}Q_{0}=011$, then its next state $\left...

Assuming that all flip-flops are in reset condition initially, the count sequence observed at $\text{Q}_\text{A}$ in the circuit shown is$0010111 \ldots$$0001011 \ldots$$...

Two $\text{D}$ flip-flops are connected as a synchronous counter that goes through the following $\mathrm{Q}_{\text{B}} \;\mathrm{Q}_{\mathrm{A}}$ sequence $00 \rightarro...

For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{\text{setup}}$ is the setup-time, and $t_{\text{hold}}$ is the hold time....