Recent questions tagged flip-flops / GO Electronics

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GATE ECE 2020 | Question: 50
For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{\text{setup}}$ is the setup-time, and $t_{\text{hold}}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is _________$\text{MHz}$.

For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{\text{setup}}$ is the setup-time, and $t_{\text{hold}}$ is the hold time....

go_editor

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go_editor asked Feb 13, 2020

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GATE ECE 2015 Set 3 | Question: 14
The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset $(\overline{R_{d}}\:\text{input}).$ The counter corresponding to this circuit is a modulo-$5$ binary up counter a modulo-$6$ binary down counter a modulo-$5$ binary down counter a modulo-$6$ binary up counter

The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset $(\overline{R_{d}}\:\text{input}).$ The counter corresponding to this circuit isa...

Milicevic3306

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Milicevic3306 asked Mar 27, 2018

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GATE ECE 2015 Set 3 | Question: 38
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing NOR gates to NAND gates inverters to buffers NOR gates to NAND gates and inverters to buffers $5\: V$ to ground

An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the cir...

Milicevic3306

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Milicevic3306 asked Mar 27, 2018

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GATE ECE 2014 Set 3 | Question: 15
The circuit shown in the figure is a Toggle Flip Flop JK Flip Flop SR Latch Master-Slave D Flip Flop

The circuit shown in the figure is a Toggle Flip FlopJK Flip FlopSR LatchMaster-Slave D Flip Flop

Milicevic3306

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Milicevic3306 asked Mar 26, 2018

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GATE ECE 2014 Set 2 | Question: 41
The outputs of the two flip-flops $Q1$, $Q2$ in the figure shown are initialized to $0,0$. The sequence generated at $Q1$ upon application of clock signal is $01110 \dots$ $01010\dots$ $00110\dots$ $01100\dots$

The outputs of the two flip-flops $Q1$, $Q2$ in the figure shown are initialized to $0,0$. The sequence generated at $Q1$ upon application of clock signal is $01110 \dots...

Milicevic3306

16.0k points

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Milicevic3306 asked Mar 26, 2018

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GATE ECE 2014 Set 1 | Question: 16
Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of $1\: MHz$ are applied as shown. The frequency $(\text{in}\:kHz)$ of the waveform at $Q3$ is ________.

Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of $1\: MHz$ are applied as shown. The frequency $(\text{in}\:kHz)$ of th...

Milicevic3306

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Milicevic3306 asked Mar 25, 2018

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GATE ECE 2018 | Question: 46
In the circuit shown below, a positive edge-triggered $D$ Flip-Flop is used for sampling input data $D_{in}$ using clock $CK$. The XOR gate output $3.3$ volts for logic HIGH and $0$ volts for logic LOW levels. The data bit and clock periods are ... period is $0.3$, the average value (in volts, accurate to two decimal places) of the voltage at node $X$, is _________.

In the circuit shown below, a positive edge-triggered $D$ Flip-Flop is used for sampling input data $D_{in}$ using clock $CK$. The XOR gate output $3.3$ volts for logic H...

gatecse

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gatecse asked Feb 19, 2018

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GATE ECE 2018 | Question: 19
A traffic signal cycles from $\text{ GREEN to YELLOW, YELLOW to RED and RED to GREEN.}$ In each cycle, $\text{GREEN}$ is turned on for $70$ seconds,$\text{YELLOW}$ is turned on for $5$ seconds and the $\text{RED}$ is turned on $75$ ... $5$ second period. The minimum number of flip-flops required to implement this $\text{FSM}$ is _________.

A traffic signal cycles from $\text{ GREEN to YELLOW, YELLOW to RED and RED to GREEN.}$ In each cycle, $\text{GREEN}$ is turned on for $70$ seconds,$\text{YELLOW}$ is tur...

gatecse

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gatecse asked Feb 19, 2018