0 0 votes A standard CMOS inverter is designed with equal rise and fall times $(\beta_{n}=\beta_{p}).$ If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin $NM_{L}$ and the HIGH noise margin $NM_{H}$? $NM_{L}$ increases and $NM_{H}$ decreases. $NM_{L}$ decreases and $NM_{H}$ increases. Both $NM_{L}$ and $NM_{H}$ increases. No change in the noise margins. Electronic Devices gate2019-ec electronic-devices cmos + – Arjun 961 views answer comment Share Follow Add Sync Questions Print 0 reply Please log in or register to add a comment.
