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GATE ECE 2025 | Question: 35

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A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input $P 0$ is set to logic '$0$ ' and $P 1$ is set to logic '$1$' at all times. The timing diagram of the inputs $S E L$ and $S$ are also shown below.

The sequence of output $Y$ from time $T_{0}$ to $T_{3}$ is _______.

  1. $1011$
  2. $0100$
  3. $0010$
  4. $1101$

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