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Recent questions and answers in Combinational Circuits
3
3 votes
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2 answers
528
528 views
GATE ECE 2026 | Question: 10
In the circuit shown in the Figure, $A$ and $B$ are logic inputs and $Y$ is the logic output.Which of the following logic operations is realized by the circuit?NORORXORAN...
Nandu972
528
views
answered
Aug 9
Combinational Circuits
gateec-2026
digital-circuits
logic-gates
combinational-circuits
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1
1 vote
1
1 answer
340
340 views
GATE ECE 2026 | Question: 38
A Boolean function, $f(x, y, z)$ with $x$ as MSB and $z$ as LSB is realized by $4: 1$ multiplexer (MUX) with select lines, $\mathrm{S}_{1}$ and $\mathrm{S}_{0}\left(\math...
akash_kumar 9
340
views
answered
Mar 11
Combinational Circuits
gateec-2026
digital-circuits
combinational-circuits
logic-gates
boolean-algebra
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0
0 votes
1
1 answer
271
271 views
GATE ECE 2026 | Question: 46
Consider the four-variable Boolean function,$f(w, x, y, z)=\sum m(0,2,5,7,8,10,13,14,15)$ with '$w$' as MSB and '$z$' as LSB.Which of the following expressions is/are the...
akash_kumar 9
271
views
answered
Mar 11
Combinational Circuits
gateec-2026
boolean-algebra
combinational-circuits
multiple-selects
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1
1 vote
1
1 answer
429
429 views
GATE ECE 2026 | Question: 17
A binary ripple counter is designed to count $(0)_{10}$ to $(64)_{10}$.Which of the following is/are the number of flip-flops required to design the counter?$6$$7$$4$$5$
akash_kumar 9
429
views
answered
Mar 11
Combinational Circuits
gateec-2026
digital-circuits
sequential-circuits
flip-flops
numerical-answers
multiple-selects
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1
1 vote
0
0 answers
124
124 views
GATE ECE 2026 | Question: 39
A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared...
gatecse
124
views
asked
Feb 23
Combinational Circuits
gateec-2026
digital-circuits
flip-flops
sequential-circuits
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3
3 votes
2
2 answers
2.4k
2.4k views
GATE ECE 2024 | Question: 9
For the Boolean function\[F(A, B, C, D)=\sum m(0,2,5,7,8,10,12,13,14,15) \text {, }\]the essential prime implicants are $\_\_\_\_\_\_$.$B D, \bar{B} \bar{D}$$B D, A B...
rashmi8303
2.4k
views
answered
Jan 29
Combinational Circuits
gateece-2024
boolean-algebra
combinational-circuits
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0
0 votes
1
1 answer
850
850 views
GATE ECE 2025 | Question: 14
A full adder and an XOR gate are used to design a digital circuit with inputs $X, Y$, and $Z$, and output $F$, as shown below. The input $Z$ is connected to the carry-in ...
Amprita
850
views
answered
Nov 17, 2025
Combinational Circuits
gateec-2025
combinational-circuits
digital-circuits
number-representation
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1
1 vote
2
2 answers
983
983 views
GATE ECE 2025 | Question: 13
A $3$-input majority logic gate has inputs $X, Y$, and $Z$. The output $F$ of the gate is logic '$1$' if two or more of the inputs are logic '$1$'. The output $F$ is logi...
Akilan_NA
983
views
answered
May 26, 2025
Combinational Circuits
gateec-2025
combinational-circuits
boolean-algebra
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0
0 votes
2
2 answers
1.2k
1.2k views
GATE ECE 1997 | Question 4.2
The decoding circuit shown in the figure is has been used to generate the active low chip select signal for a microprocessor peripheral. (The address lines are designated...
dertfghjlk
1.2k
views
answered
Dec 15, 2024
Combinational Circuits
gate1997-ec
combinational-circuits
computer-organization
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4
4 votes
1
1 answer
3.9k
3.9k views
GATE ECE 2023 | Question: 24
For the circuit shown below, the propagation delay of each $ \mathrm{NAND}$ gate is $1 \mathrm{~ns}$. The critical path delay, in $\text{ns,}$ is______________(rounded of...
Deepak Poonia
3.9k
views
answered
Jul 1, 2024
Combinational Circuits
gateece-2023
combinational-circuits
numerical-answers
digital-circuits
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3
3 votes
1
answers
1 answer
988
988 views
GATE ECE 2009 | Question: 38
Refer to the NAND and NOR latches shown in the figure. The inputs $\left(P_{1}, P_{2}\right)$ for both the latches are first made $(0,1)$ and then, after a few seconds, m...
Deepak Poonia
988
views
answered
Jul 1, 2024
Combinational Circuits
gate2009-ec
sequential-circuits
logic-gates
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1
1 vote
1
1 answer
1.1k
1.1k views
GATE ECE 2022 | Question: 9
Consider the $ \text{2–bit}$ multiplexer $\text{(MUX)}$ shown in the figure. For $\text{OUTPUT}$ to be the $\text{XOR}$ of $\text{C}$ and $\text{D},$ the values for $A_{0...
Deepak Poonia
1.1k
views
answered
Oct 23, 2023
Combinational Circuits
gateece-2022
multiplexers
combinational-circuits
digital-circuits
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3
3 votes
1
1 answer
2.1k
2.1k views
GATE ECE 2010 | Question: 12
For the output $\text{F}$ to be $1$ in the logic circuit shown, the input combination should be$\mathrm{A}=1, \mathrm{~B}=1, \mathrm{C}=0$$\text{A = 1, B = 0, C = 0}$$\ma...
Deepak Poonia
2.1k
views
answered
Oct 10, 2023
Combinational Circuits
gate2010-ec
digital-circuits
combinational-circuits
logic-gates
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2
2 votes
1
1 answer
1.4k
1.4k views
GATE ECE 2010 | Question: 11
Match the logic gates in Column A with their equivalents in Column B.$\text{P-2, Q-4, R-1, S-3}$$\text{P-4, Q-2, R-1, S-3}$$\text{P-2, Q-4, R-3, S-1}$$\text{P-4, Q-2, R-3...
Deepak Poonia
1.4k
views
answered
Oct 7, 2023
Combinational Circuits
gate2010-ec
digital-circuits
combinational-circuits
logic-gates
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2
2 votes
1
answers
1 answer
2.4k
2.4k views
GATE ECE 2022 | Question: 39
Consider a Boolean gate $\text{(D)}$ where the output $Y$ is related to the inputs $A$ and $B$ as, $Y = A + \overline{B},$ where $+$ denotes logical $\text{OR}$ operation...
Deepak Poonia
2.4k
views
answered
Oct 7, 2023
Combinational Circuits
gateece-2022
multiple-selects
functional-completeness
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2
2 votes
1
1 answer
1.2k
1.2k views
GATE ECE 2022 | Question: 17
Select the Boolean function(s) equivalent to $x+yz,$ where $x, y,$ and $z$ are Boolean variables, and $+$ denotes logical $\text{OR}$ operation.$x + z + xy$$(x + y)(x + z...
Deepak Poonia
1.2k
views
answered
Oct 6, 2023
Combinational Circuits
gateece-2022
boolean-algebra
combinational-circuits
multiple-selects
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0
0 votes
0
0 answers
473
473 views
GATE ECE 1997 | Question 2.6
A $2$ bit binary multiplier can be implemented using$2$ inputs $\text{ANDs}$ only$2$ input $\text{XOR s}$ and $4$ input $\text{AND}$ gates onlyTwo $2$ inputs $\text{NORs}...
admin
473
views
asked
Oct 2, 2022
Combinational Circuits
gate1997-ec
combinational-circuits
digital-circuits
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–
0
0 votes
0
0 answers
554
554 views
GATE ECE 1997 | Question 2.7
In standard $\text{TTL}$, the 'totem pole' stage refers tothe multi-emitter input stagethe phase splitterthe output bufferopen collector output stage
admin
554
views
asked
Oct 2, 2022
Combinational Circuits
gate1997-ec
digital-circuits
logic-gates
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–
0
0 votes
0
0 answers
513
513 views
GATE ECE 1997 | Question 2.8
The inverter $74 \; \mathrm{ALSO} 4$ has the following specifications\[ \begin{array}{l}\mathrm{I}_{\text {OH } \max }=-0.4 \mathrm{~mA}, \mathrm{l}_{\text {OLmax }}=8 \m...
admin
513
views
asked
Oct 2, 2022
Combinational Circuits
gate1997-ec
digital-circuits
numerical-answers
+
–
0
0 votes
0
0 answers
497
497 views
GATE ECE 1997 | Question 2.9
The output of the logic gate in the figure is$0$$1$$\text{A}$$\mathrm{F}$
admin
497
views
asked
Oct 2, 2022
Combinational Circuits
gate1997-ec
logic-gates
combinational-circuits
+
–
1
1 vote
0
0 answers
468
468 views
GATE ECE 1997 | Question 4.7
For the $\text{NMOS}$ logic gate shown in the figure is the logic function implemented is$\overline{\mathrm{ABCDE}}$$(\mathrm{AB}+\overline{\mathrm{C}}) \cdot(\overline{\...
admin
468
views
asked
Oct 2, 2022
Combinational Circuits
gate1997-ec
combinational-circuits
digital-circuits
logic-gates
+
–
0
0 votes
0
0 answers
348
348 views
GATE ECE 1997 | Question 4.9
The gate delay of an $\text{NMOS}$ inverter is dominated by charge time rather than discharge time becausethe driver transistor has larger threshold voltage than the load...
admin
348
views
asked
Oct 2, 2022
Combinational Circuits
gate1997-ec
mosfet
digital-circuits
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3
3 votes
0
0 answers
329
329 views
GATE ECE 1997 | Question 4.10
The boolean function $\mathrm{A}+\mathrm{BC}$ is a reduced form of$\mathrm{AB}+\mathrm{BC}$$(\mathrm{A}+\mathrm{B}) \cdot(\mathrm{A}+\mathrm{C})$$\overline{\mathrm{A}} \m...
admin
329
views
asked
Oct 2, 2022
Combinational Circuits
gate1997-ec
combinational-circuits
boolean-algebra
+
–
1
1 vote
0
0 answers
426
426 views
GATE ECE 2000 | Question 1.19
For the logic circuit shown in the figure is the required input condition $(A, B, C)$ to make the output $(X)=1$ is$1,0,1$$0,0,1$$1,1,1$$0,1,1$
admin
426
views
asked
Sep 29, 2022
Combinational Circuits
gate2000-ec
logic-gates
combinational-circuits
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–
1
1 vote
0
0 answers
601
601 views
GATE ECE 2000 | Question 2.7
For the logic circuit shown in, the simplified Boolean expression for the output $Y$ is$\mathrm{A}+\mathrm{B}+\mathrm{C}$$\mathrm{A}$$\mathrm{B}$$\mathrm{C}$
admin
601
views
asked
Sep 29, 2022
Combinational Circuits
gate2000-ec
combinational-circuits
boolean-algebra
+
–
0
0 votes
0
0 answers
352
352 views
GATE ECE 2000 | Question 15
The operating conditions $(O N=1, O F F=0)$ of three pumps $(x, y, z)$ are to be monitored. $x=1$ implies that pump $X$ is on. It is required that the indicator $\text{(L...
admin
352
views
asked
Sep 29, 2022
Combinational Circuits
gate2000-ec
combinational-circuits
logic-gates
boolean-algebra
circuit-analysis
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–
0
0 votes
0
0 answers
303
303 views
GATE ECE 2000 | Question 16
A one-bit full adder is to be implemented using $8$-to-$1$ multiplexers $\text{(MUX)}$.Write the truth table for sum $\text{(S)}$ and carry to the next stage $\left(\math...
admin
303
views
asked
Sep 29, 2022
Combinational Circuits
gate2000-ec
combinational-circuits
multiplexers
number-system
+
–
0
0 votes
0
0 answers
358
358 views
GATE ECE 1999 | Question 1.10
The logical expresion $y=\mathrm{A}+\overline{\mathrm{A}} \mathrm{B} $ is equivalent to$y=\mathrm{AB}$$y=\overline{\mathrm{A}} \mathrm{B}$$y=\bar{A}+\mathrm{B}$$y=\mathr...
admin
358
views
asked
Sep 29, 2022
Combinational Circuits
gate1999-ec
boolean-algebra
logic-gates
combinational-circuits
+
–
0
0 votes
0
0 answers
437
437 views
GATE ECE 1999 | Question 1.12
Commercially available $\text{ECL}$ gears use two ground lines and one negative supply in order toreduce power dissipationincrease fan-outreduce loading effecteliminate t...
admin
437
views
asked
Sep 29, 2022
Combinational Circuits
gate1999-ec
digital-circuits
+
–
0
0 votes
0
0 answers
325
325 views
GATE ECE 1999 | Question 2.10
The minimized form of the logical expression $(\bar{A} \bar{B} \bar{C}+\bar{A} B \bar{C}+\bar{A} B C+A B \bar{C})$ is$\overline{\mathrm{A}} \overline{\mathrm{C}}+\mathrm{...
admin
325
views
asked
Sep 29, 2022
Combinational Circuits
gate1999-ec
combinational-circuits
boolean-algebra
+
–
0
0 votes
0
0 answers
357
357 views
GATE ECE 1999 | Question 2.11
For a binary half-subtractor having two inputs $\text{A}$ and $\text{B}$, the correct set of logical expressions for the outputs $\text{D}$ ( = $\text{A}$ minus $\text{B}...
admin
357
views
asked
Sep 29, 2022
Combinational Circuits
gate1999-ec
combinational-circuits
logic-gates
numerical-answers
+
–
0
0 votes
0
0 answers
472
472 views
GATE ECE 1999 | Question 12
In a certain application, four inputs $A, B, C, D$ (both true and complement forms available) are fed to logic circuit, producing an output $F$ which operates a relay. Th...
admin
472
views
asked
Sep 29, 2022
Combinational Circuits
gate1999-ec
combinational-circuits
logic-gates
boolean-algebra
+
–
0
0 votes
0
0 answers
290
290 views
GATE ECE 2001 | Question: 1.11
Consider the following two statements :$\text{Statement 1: A}$ stable multivibrator can be used for generating square wave.$\text{Statement 1: B}$ stable multivibrator c...
admin
290
views
asked
Sep 29, 2022
Combinational Circuits
gate2001-ec
analog-circuits
combinational-circuits
+
–
0
0 votes
0
0 answers
751
751 views
GATE ECE 2001 | Question: 2.11
In the TTL circuit in the figure, $\mathrm{S}_{2}$ to $\mathrm{S}_{0}$ are select lines and $\text{X}_{7}$ to $\text{X}_{0}$ are input lines. $\text{S}_{0}$ and $\text{X}...
admin
751
views
asked
Sep 29, 2022
Combinational Circuits
gate2001-ec
combinational-circuits
digital-circuits
logic-gates
+
–
1
1 vote
0
0 answers
620
620 views
GATE ECE 2001 | Question: 2.12
The digital block in the figure, realized using two positive edge triggered D-flip-flops. Assume that for that for $t < t_{0}, Q_{1} =Q_{2} = 0.$ The circuit in the digit...
admin
620
views
asked
Sep 29, 2022
Combinational Circuits
gate2001-ec
sequential-circuits
flip-flops
digital-circuits
+
–
0
0 votes
0
0 answers
329
329 views
GATE ECE 2001 | Question: 11
For the digital block shown in the figure the output $\mathrm{Y}=f\left(\mathrm{~S}_{3}, \mathrm{~S}_{2}, \mathrm{~S}_{1}, \mathrm{~S}_{0}\right)$ where $\mathrm{S}_{3}$ ...
admin
329
views
asked
Sep 29, 2022
Combinational Circuits
gate2001-ec
combinational-circuits
boolean-algebra
logic-gates
+
–
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