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Recent questions tagged sequential-circuits

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GATE ECE 2026 | Question: 17
A binary ripple counter is designed to count $(0)_{10}$ to $(64)_{10}$.Which of the following is/are the number of flip-flops required to design the counter?$6$$7$$4$$5$
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GATE ECE 2026 | Question: 25
The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a square wave of $10$ cycles/second is applied to its clock (C) input.The...
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GATE ECE 2026 | Question: 39
A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared...
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GATE ECE 2025 | Question: 35
A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input $P 0$ is set to logic '$0$ ' and $P 1$ is set to logic '...
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GATE ECE 2025 | Question: 52
In the circuit shown below, the $\mathrm{AND}$ gate has a propagation delay of $1 \: \mathrm{ ns}$. The edge-triggered flip-flops have a set-up time of $2 \: \mathrm{ ns}...
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GATE ECE 2023 | Question: 14
The synchronous sequential circuit shown below works at a clock frequency $1 \; \mathrm{GHz}$. The throughput, in $\text{Mbits/s,}$ and the latency, in $\text{ns,}$ respe...
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GATE ECE 2023 | Question: 53
In a given sequential circuit, initial states are $Q_1=1$ and $Q_2=0$. For a clock frequency of $1 \; \mathrm{MHz}$, the frequency of signal $\mathrm{Q}_2$ in $\mathrm{kH...
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GATE ECE 1997 | Question 4.8
In a $\text{J-K}$ flip-flip we have $\text{J} = \overline{Q}$ and $\text{K}=1$. Assuming the flip-flop was initially cleared and then clocked for $6$ puleses, the sequenc...
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GATE ECE 1997 | Question 5.3
(1) An $8$-bit wide $5$ word sequential memory will have$8$ Fixed $\text{‘AND'}$ gates and $4$ programmable $\text{‘OR'}$ gates(2) A $256 \times 4$ $\text{EFROM}$ hasEigh...
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GATE ECE 1997 | Question 7
Circuit shown in the figure is an $\text{NMOS}$ shift register. All transistors are $\text{NMOS}$ enhancement type with threshold voltage $V_{T}=1 \mathrm{~V}$. Supply us...
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GATE ECE 1997 | Question 14
A sequence generator is shown in the figure. The counter status $\left(\mathrm{Q}_{0}, \mathrm{Q}_{1}, \mathrm{Q}_{2}\right)$ is initialised to $010$ using preset/clear i...
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GATE ECE 2000 | Question 2.9
A sequential circuit using $D$ Flip-Flop and logic gates is shown in figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is$S-R$ Flip-Flop with in...
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GATE ECE 2000 | Question 2.11
In given figure, the $J$ and $K$ inputs of all the four Flip-Flips are made high. The frequency of the signal at output $Y$ is$0.833 \; \mathrm{kHz}$$1.0 \; \mathrm{kHz}$...
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GATE ECE 1999 | Question 2.12
The ripple counter shown in the given figure works as a$\bmod -3$ up counter$\bmod -5$ up counter$\bmod - 3$ down counter$\bmod - 5$ down counter
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GATE ECE 1999 | Question 11
The circuit diagram of a synchronous counter is shown in the given figure. Determine the sequence of states of the counter assuming that the initial state is '$000$'. Giv...
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GATE ECE 2001 | Question: 2.12
The digital block in the figure, realized using two positive edge triggered D-flip-flops. Assume that for that for $t < t_{0}, Q_{1} =Q_{2} = 0.$ The circuit in the digit...
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GATE ECE 2001 | Question: 10
In the figure, the output of the oscillator, $\mathrm{V}_{1}$ has $10 \mathrm{~V}$ peak amplitude with zero DC value. The transfer characteristic of the Schmitt inverter ...
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GATE ECE 2002 | Question: 2.10
The circuit in the figure is has two $\text{CMOS NOR}$-gates. This circuit functions as aflip-flopschmitt triggernonostable multivibratorastable multivibrator
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GATE ECE 2002 | Question: 11
It is required to design a binary mod-$5$ synchronous counter using $\text{AB}$ flip-flops such that the output $Q_{2} Q_{1} Q_{0}$ changes as $000 \rightarrow 001 \right...
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GATE ECE 1998 | Question 2.3
In the figure is $A=1$ and $B=1$, the input $B$ is now replaced by a sequence $101010 \ldots$. , the outputs $x$ and $y$ will befixed at $0$ and $1$, respectively$x=1010 ...
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GATE ECE 1998 | Question 2.11
The figure shows a mod-$\mathrm{K}$ counter, here $\mathrm{K}$ is equal to$1$$2$$3$$4$
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GATE ECE 1998 | Question 15
The $\text{mod}-5$ counter shown in the figure is counts through states $Q_{2} Q_{1} Q_{0}=000,001,010,011$ and $100$(a) Will the counter lockout if it happen to be in an...
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GATE ECE 2003 | Question: 20
A $0$ to $6$ counter consists of $3$ flip flops and a combination circuit of $2$ input gate(s). The combination circuit consists ofone AND gateone OR gateone AND gate and...
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GATE ECE 2003 | Question: 55
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip flops having a propagation delay of $10 \mathrm{~ns}$ each. If the worst case delay in the ...
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GATE ECE 2003 | Question: 59
In the circuit shown in the figure $\mathrm{A}$ is a parallel-in, parallel-out $4$ bit register, which loads at the rising edge of the clock $C$. The input lines are conn...
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GATE ECE 2004 | Question: 13
A master-slave flip-flop has the characteristic thatchange in the input immediately reflected in the outputchange in the output occurs when the state of the master is aff...
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GATE ECE 2004 | Question: 16
Choose the correct one from among the alternatives $\text{A, B, C, D}$ after matching an item from Group $1$ with the most appropriate item in Group $2.$$$\begin{array}{|...
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GATE ECE 2004 | Question: 56
In the modulo-$6$ ripple counter shown in the given figure, the output of the $2$-input gate is used to clear the J-K flip-flops.The $2$-input gate isa NAND gatea NOR gat...
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GATE ECE 2005 | Question: 56
The present output $Q_{n}$ of an edge triggered JK flip-flop is logic $0.$ If $\mathrm{J}=1$, then $\mathrm{Q}_{n+1}$cannot be determinedwill be logic $0$will be logic $1...
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GATE ECE 2005 | Question: 57
The given figure shows a ripple counter using positive edge triggered flip-flops. If the present state of the counter is $Q_{2}Q_{1}Q_{0}=011$, then its next state $\left...
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