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Questions without answers in Analog Circuits

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GATE ECE 2016 Set 3 | Question: 14
Consider the circuit shown in the figure. Assuming $V_{EE1} = V_{EE2} = 0.7$ volt, the value of the dc voltage $V_{C2}$(in volt) is _______
Consider the circuit shown in the figure. Assuming $V_{EE1} = V_{EE2} = 0.7$ volt, the value of the dc voltage $V_{C2}$(in volt) is _______
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GATE ECE 2016 Set 3 | Question: 15
In the astable multivibrator circuit shown in the figure, the frequency of oscillation (in kHz) at the output pin $3$ is _______
In the astable multivibrator circuit shown in the figure, the frequency of oscillation (in kHz) at the output pin $3$ is _______
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GATE ECE 2016 Set 2 | Question: 11
The Ebers-Moll model of a $BJT$ is valid only in active mode only in active and saturation modes only in active and cut-off modes in active, saturation and cut-off modes
The Ebers-Moll model of a $BJT$ is valid only in active modeonly in active and saturation modesonly in active and cut-off modesin active, saturation and cut-off modes
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GATE ECE 2016 Set 1 | Question: 17
The output of the combinational circuit given below is $A+B+C$ $A(B+C)$ $B(C+A)$ $C(A+B)$
The output of the combinational circuit given below is $A+B+C$$A(B+C)$$B(C+A)$$C(A+B)$
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GATE ECE 2016 Set 1 | Question: 18
What is the voltage $V_{out}$ in the following circuit ? $0 V$ ($\mid V_T$ of PMOS$\mid$ + $V_T$ of NMOS)$/2$ Switching threshold of inverter $V_{DD}$
What is the voltage $V_{out}$ in the following circuit ?$0 V$($\mid V_T$ of PMOS$\mid$ + $V_T$ of NMOS)$/2$Switching threshold of inverter$V_{DD}$
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GATE ECE 2016 Set 1 | Question: 33
An AC voltage source $V = 10 \sin(t)$ volts is applied to the following network. Assume that $R_1 = 3 k\Omega$, $R_2 = 6 k\Omega$ and $R_3 = 9k\Omega$, and that the diode is ideal. RMS current $I_{rms}$(in mA) through the diode is _______
An AC voltage source $V = 10 \sin(t)$ volts is applied to the following network. Assume that $R_1 = 3 k\Omega$, $R_2 = 6 k\Omega$ and $R_3 = 9k\Omega$, and that the diode...
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GATE ECE 2016 Set 1 | Question: 34
In the circuit shown in the figure, the maximum power (in watt) delivered to the resistor $R$ is _______
In the circuit shown in the figure, the maximum power (in watt) delivered to the resistor $R$ is _______
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GATE ECE 2015 Set 3 | Question: 9
In the circuit shown, the voltage $V_{X}$ (in Volts) is ________.
In the circuit shown, the voltage $V_{X}$ (in Volts) is ________.
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GATE ECE 2015 Set 3 | Question: 8
At very high frequencies, the peak output voltage $V_{0}$ (in Volts) is _______.
At very high frequencies, the peak output voltage $V_{0}$ (in Volts) is _______.
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31
GATE ECE 2015 Set 3 | Question: 9
Which one of the following processes is preferred to form the gate dielectric $(SiO_{2})$ of MOSFETs ? Sputtering Molecular beam epitaxy Wet oxidation Dry oxidation
Which one of the following processes is preferred to form the gate dielectric $(SiO_{2})$ of MOSFETs ? Sputtering Molecular beam epitaxy Wet oxidation Dry oxidation
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32
GATE ECE 2015 Set 3 | Question: 10
If the base width in a bipolar junction transistor is doubled, which one of the following statements will be TRUE? Current gain will increase Unity gain frequency will increase Emitter-base junction capacitance will increase Early Voltage will increase
If the base width in a bipolar junction transistor is doubled, which one of the following statements will be TRUE? Current gain will increase Unity gain frequency will in...
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GATE ECE 2015 Set 3 | Question: 11
In the circuit shown in the figure, the BJT has a current gain $(\beta)$ of $50.$ For an emitter-base voltage ܸ $V_{EB} = 600\: mV,$ the emitter-collector voltage $V_{EC}$ (in Volts) is _______.
In the circuit shown in the figure, the BJT has a current gain $(\beta)$ of $50.$ For an emitter-base voltage ܸ $V_{EB} = 600\: mV,$ the emitter-collector voltage $V_{EC...
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GATE ECE 2015 Set 3 | Question: 12
In the circuit shown using an ideal opamp, the $3$-dB cut-off frequency (in Hz) is _______.
In the circuit shown using an ideal opamp, the $3$-dB cut-off frequency (in Hz) is _______.
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35
GATE ECE 2015 Set 3 | Question: 13
In the circuit shown, assume that diodes $D_{1}$ and $D_{2}$ are ideal. In the steady state condition, the average voltage $V_{ab}$ (in Volts) across the $0.5\: \mu F$ capacitor is ______.
In the circuit shown, assume that diodes $D_{1}$ and $D_{2}$ are ideal. In the steady state condition, the average voltage $V_{ab}$ (in Volts) across the $0.5\: \mu F$ ca...
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GATE ECE 2015 Set 3 | Question: 18
Consider a four-point moving average filter defined by the equation $y[n] = \displaystyle{}\sum _{i=0}^{3}\alpha_{i}\:x[n-i].$ ... $\alpha_{1} = \alpha_{2} = 0;\:\alpha_{0} = \alpha_{3}$
Consider a four-point moving average filter defined by the equation $y[n] = \displaystyle{}\sum _{i=0}^{3}\alpha_{i}\:x[n-i].$ The condition on the filter coefficients t...
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GATE ECE 2015 Set 3 | Question: 39
In the circuit shown, assume that the opamp is ideal. If the gain $(v_{0} / v_{in})$ is $–12,$ the value of $R\: (\text{in}\: k\Omega)$ is _____.
In the circuit shown, assume that the opamp is ideal. If the gain $(v_{0} / v_{in})$ is $–12,$ the value of $R\: (\text{in}\: k\Omega)$ is _____.
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