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Questions without answers in Digital Circuits
1
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1
GATE ECE 2011 | Question: 41
Two $\text{D}$ flip-flops are connected as a synchronous counter that goes through the following $\mathrm{Q}_{\text{B}} \;\mathrm{Q}_{\mathrm{A}}$ sequence $00 \rightarrow 11 \rightarrow 01 \rightarrow 10 \rightarrow 00 \rightarrow \cdots$ The connections to the ...
Two $\text{D}$ flip-flops are connected as a synchronous counter that goes through the following $\mathrm{Q}_{\text{B}} \;\mathrm{Q}_{\mathrm{A}}$ sequence $00 \rightarro...
admin
46.4k
points
36
views
admin
asked
Sep 3, 2022
Sequential Circuits
gate2011-ec
digital-circuits
sequential-circuit
flip-flop
+
–
0
votes
0
answers
2
GATE ECE 2021 | Question: 12
Addressing of a $32K\:\times\:16$ memory is realized using a single decoder. The minimum number of $\text{AND}$ gates required for the decoder is $2^{8}$ $2^{32}$ $2^{15}$ $2^{19}$
Addressing of a $32K\:\times\:16$ memory is realized using a single decoder. The minimum number of $\text{AND}$ gates required for the decoder is$2^{8}$...
Arjun
6.6k
points
192
views
Arjun
asked
Feb 19, 2021
Digital Circuits
gateec-2021
digital-circuits
combinational-circuits
decoders
+
–
0
votes
0
answers
3
GATE ECE 2021 | Question: 31
The propagation delays of the $\text{XOR}$ gate, $\text{AND}$ gate and multiplexer $\text{(MUX)}$ in the circuit shown in the figure are $4\:ns$, $2\:ns$ and $1\:ns$, respectively. If all the inputs $\text{P, Q, R, S and T}$ are applied simultaneously and held constant, the maximum propagation delay of the circuit is $3\:ns$ $5\:ns$ $6\:ns$ $7\:ns$
The propagation delays of the $\text{XOR}$ gate, $\text{AND}$ gate and multiplexer $\text{(MUX)}$ in the circuit shown in the figure are $4\:ns$, $2\...
Arjun
6.6k
points
669
views
Arjun
asked
Feb 19, 2021
Digital Circuits
gateec-2021
digital-circuits
combinational-circuits
multiplexers
+
–
0
votes
0
answers
4
GATE ECE 2021 | Question: 46
The propagation delay of the exclusive$-\text{OR}$ ($\text{XOR}$) gate in the circuit in the figure is $3\:ns$. The propagation delay of all the flip-flops is assumed to be zero. The clock ($\text{Clk}$ ... of triggering clock edges after which the flip-flop outputs $Q_{2}Q_{1}Q_{0}$ becomes $1\; 0\; 0$ (in integer) is
The propagation delay of the exclusive$-\text{OR}$ ($\text{XOR}$) gate in the circuit in the figure is $3\:ns$. The propagation delay of all the flip-flops is assumed to ...
Arjun
6.6k
points
379
views
Arjun
asked
Feb 19, 2021
Digital Circuits
gateec-2021
numerical-answers
digital-circuits
sequential-circuit
counters
+
–
0
votes
0
answers
5
GATE ECE 2020 | Question: 6
A single crystal intrinsic semiconductor is at a temperature of $300$ $\text{K}$ with effective density of states for holes twice that of electrons. The thermal voltage is $26$ mV. The intrinsic Fermi level is shifted from mid-bandgap energy level by $18.02 \: meV$ $9.01 \: meV$ $13.45 \: meV$ $26.90 \: meV$
A single crystal intrinsic semiconductor is at a temperature of $300$ $\text{K}$ with effective density of states for holes twice that of electrons. The thermal voltage i...
go_editor
1.9k
points
221
views
go_editor
asked
Feb 13, 2020
Digital Circuits
gate2020-ec
digital-circuits
semiconductor
+
–
0
votes
0
answers
6
GATE ECE 2020 | Question: 19
In an $8085$ microprocessor, the number of address lines required to access a $16$ K byte memory bank is ____________ .
In an $8085$ microprocessor, the number of address lines required to access a $16$ K byte memory bank is ____________ .
go_editor
1.9k
points
142
views
go_editor
asked
Feb 13, 2020
Digital Circuits
gate2020-ec
numerical-answers
digital-circuits
microprocessor-8085
+
–
0
votes
0
answers
7
GATE ECE 2020 | Question: 20
A $10$-bit D/A converter is calibrated over the full range from $0$ to $10$ V. If the input to the D/A converter is $13 \:A$ (in hex), the output ( rounded off to three decimal places) is __________ $V$.
A $10$-bit D/A converter is calibrated over the full range from $0$ to $10$ V. If the input to the D/A converter is $13 \:A$ (in hex), the output ( rounded off to three d...
go_editor
1.9k
points
188
views
go_editor
asked
Feb 13, 2020
Digital Circuits
gate2020-ec
numerical-answers
digital-circuits
data-converters
+
–
0
votes
0
answers
8
GATE ECE 2020 | Question: 32
The band diagram of a $p$-type semiconductor with a band-gap of $1$ eV is shown. Using this semiconductor, a $\text{MOS}$ capacitor having $V_{TH}$ of $-0.16 V$, ${C}'_{ox}$ of $100\:nF/cm^{2}$ and a metal work function of $3.87 \: eV$ is fabricated. There is no ... $1.70\times 10^{-8}$ $0.52\times 10^{-8}$ $1.41\times 10^{-8}$ $0.93\times 10^{-8}$
The band diagram of a $p$-type semiconductor with a band-gap of $1$ eV is shown. Using this semiconductor, a $\text{MOS}$ capacitor having $V_{TH}$ of $-0.16 V$, ${C}'_{o...
go_editor
1.9k
points
185
views
go_editor
asked
Feb 13, 2020
Number Representations
gate2020-ec
digital-circuits
semiconductor
+
–
0
votes
0
answers
9
GATE ECE 2019 | Question: 14
In the circuit shown, what are the values of $F$ for $EN=0$ and $EN=1,$ respectively? $\text{0 and D}$ $\text{Hi-Z and D}$ $\text{0 and 1}$ $\text{Hi-Z and}$ $ \overline{D}$
In the circuit shown, what are the values of $F$ for $EN=0$ and $EN=1,$ respectively?$\text{0 and D}$$\text{Hi-Z and D}$$\text{0 and 1}$$\text{Hi-Z and}$ $ \overline{D}$
Arjun
6.6k
points
175
views
Arjun
asked
Feb 12, 2019
Digital Circuits
gate2019-ec
digital-circuits
logic-gates
+
–
0
votes
0
answers
10
GATE ECE 2019 | Question: 15
In the circuit shown, $A$ and $B$ are the inputs and $F$ is the output. What is the functionality of the circuit? Latch XNOR SRAM Cell XOR
In the circuit shown, $A$ and $B$ are the inputs and $F$ is the output. What is the functionality of the circuit?LatchXNORSRAM CellXOR
Arjun
6.6k
points
185
views
Arjun
asked
Feb 12, 2019
Digital Circuits
gate2019-ec
digital-circuits
logic-gates
+
–
0
votes
0
answers
11
GATE ECE 2016 Set 3 | Question: 10
The $I-V$ characteristics of three types of diodes at the room temperature, made of semiconductors $X, Y$ and $Z$, are shown in the figure. Assume that the diodes are uniformly doped and identical in all respects except their materials. If $E_{gX}$,$E_{gY}$ ... $E_{gX}=E_{gY}=E_{gZ}$ $E_{gX}<E_{gY}<E_{gZ}$ no relationship among these band gaps exists.
The $I-V$ characteristics of three types of diodes at the room temperature, made of semiconductors $X, Y$ and $Z$, are shown in the figure. Assume that the diodes are uni...
Milicevic3306
16.0k
points
177
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2016-ec-3
digital-circuits
semiconductor
+
–
0
votes
0
answers
12
GATE ECE 2016 Set 3 | Question: 16
In an $8085$ microprocessor, the contents of the accumulator and the carry flag are $A7$ (in hex) and $0$, respectively. If the instruction $RLC$ is executed, then the contents of the accumulator (in hex) and the carry flag, respectively, will be $4E$ and $0$ $4E$ and $1$ $4F$ and $0$ $4F$ and $1$
In an $8085$ microprocessor, the contents of the accumulator and the carry flag are $A7$ (in hex) and $0$, respectively. If the instruction $RLC$ is executed, then the co...
Milicevic3306
16.0k
points
123
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2016-ec-3
digital-circuits
microprocessor-8085
+
–
0
votes
0
answers
13
GATE ECE 2016 Set 3 | Question: 17
The logic functionality realized by the circuit shown below is $OR$ $XOR$ $NAND$ $AND$
The logic functionality realized by the circuit shown below is $OR$$XOR$$NAND$$AND$
Milicevic3306
16.0k
points
186
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2016-ec-3
digital-circuits
combinational-circuits
logic-gates
+
–
0
votes
0
answers
14
GATE ECE 2016 Set 3 | Question: 18
The minimum number of $2$-input $NAND$ gates required to implement a $2$-input $XOR$ gate is $4$ $5$ $6$ $7$
The minimum number of $2$-input $NAND$ gates required to implement a $2$-input $XOR$ gate is$4$$5$$6$$7$
Milicevic3306
16.0k
points
131
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2016-ec-3
digital-circuits
combinational-circuits
logic-gates
+
–
0
votes
0
answers
15
GATE ECE 2016 Set 3 | Question: 44
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2$ ns, $1.5$ ns and $1$ ns, respectively. If all the inputs $P, Q, R, S$ and $T$ are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is _________
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2$ ns, $1.5$ ns and $1$ ns, respectively. If all the inputs $P, Q, R, S$ and...
Milicevic3306
16.0k
points
226
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2016-ec-3
numerical-answers
digital-circuits
combinational-circuits
logic-gates
+
–
0
votes
0
answers
16
GATE ECE 2016 Set 3 | Question: 45
For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a $\text{mod}-5\:\text{counter}$ $\text{mod}-6\:\text{counter}$ $\text{mod}-7\:\text{counter}$ $\text{mod}-8\:\text{counter}$
For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$...
Milicevic3306
16.0k
points
218
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2016-ec-3
digital-circuits
sequential-circuit
counters
+
–
0
votes
0
answers
17
GATE ECE 2016 Set 2 | Question: 17
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flip-flops $D_{1} \:, D_{2} \:, D_{3} \:, D_{4}$ and $D_{5}$ are initialized with ... $0$, respectively. The clocks has a $30\%$ duty cycle. The average power dissipated (in $mW$) in the resistor $R$ is _________
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flip-flops $D_{1} \:, ...
Milicevic3306
16.0k
points
372
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2016-ec-2
numerical-answers
digital-circuits
sequential-circuit
counters
+
–
0
votes
0
answers
18
GATE ECE 2016 Set 2 | Question: 18
A $4:1$ multiplexer is to be used for generating the output carry of a full adder. $A$ and $B$ are the bits to be added while $C_{in}$ is the input carry and $C_{out}$ is the output carry. $A$ and $B$ are to be used as the select bits with $A$ being the more significant select ... $I_{3}=C_{in}$ $I_{0}=0, I_{1}=C_{in},I_{2}=1$ and $I_{3}=C_{in}$
A $4:1$ multiplexer is to be used for generating the output carry of a full adder. $A$ and $B$ are the bits to be added while $C_{in}$ is the input carry and $C_{out}$ is...
Milicevic3306
16.0k
points
136
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2016-ec-2
digital-circuits
combinational-circuits
multiplexers
+
–
0
votes
0
answers
19
GATE ECE 2016 Set 2 | Question: 42
An $8$ Kbyte ROM with an active low Chip Select input $\left (\overline{CS}\right )$ is to be used in an $8085$ microprocessor based system. The ROM should occupy the address range $1000H$ to $2FFFH$. The address lines are designated as $A_{15}$ to $A_{0}$, ... $\overline{A_{15}}+ \overline{A_{14}}+A_{13} \cdot A_{12}$
An $8$ Kbyte ROM with an active low Chip Select input $\left (\overline{CS}\right )$ is to be used in an $8085$ microprocessor based system. The ROM should occupy the add...
Milicevic3306
16.0k
points
98
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2016-ec-2
digital-circuits
microprocessor
rom
+
–
0
votes
0
answers
20
GATE ECE 2016 Set 2 | Question: 43
In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source $V_{in}$ ... maximum sampling rate? $1$ megasamples per second $6$ megasamples per second $64$ megasamples per second $256$ megasamples per second
In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digita...
Milicevic3306
16.0k
points
221
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2016-ec-2
digital-circuits
analog-to-digital-converter
+
–
0
votes
0
answers
21
GATE ECE 2016 Set 2 | Question: 44
The state transition diagram for a finite state machine with states $A$, $B$ and $C$, and binary inputs $X$, $Y$ and $Z$, is shown in the figure. Which one of the following statements is correct? Transitions from State ... State $B$ are ambiguously defined. Transitions from State $C$ are ambiguously defined. All of the state transitions are defined unambiguously.
The state transition diagram for a finite state machine with states $A$, $B$ and $C$, and binary inputs $X$, $Y$ and $Z$, is shown in the figure. ...
Milicevic3306
16.0k
points
358
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2016-ec-2
digital-circuits
state-transition-diagram
+
–
0
votes
0
answers
22
GATE ECE 2016 Set 1 | Question: 11
A small percentage of impurity is added to an intrinsic semiconductor at $300 \: K$. Which one of the following statements is true for the energy band diagram shown in the following figure? Intrinsic semiconductor doped with pentavalent ... atoms to form $p$-type semiconductor. Intrinsic semiconductor doped with trivalent atoms to form $p$-type semiconductor.
A small percentage of impurity is added to an intrinsic semiconductor at $300 \: K$. Which one of the following statements is true for the energy band diagram shown in th...
Milicevic3306
16.0k
points
153
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2016-ec-1
digital-circuits
semiconductor
+
–
0
votes
0
answers
23
GATE ECE 2016 Set 1 | Question: 12
Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET): As channel length reduces,OFF-state current increases. As channel length reduces,output resistance increases. As channel length reduces,threshold voltage remains constant. As channel ... . Which of the above statements are INCORRECT? P and Q P and S Q and R R and S
Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET):As channel length reduces,OFF-state current increases.As channel length...
Milicevic3306
16.0k
points
167
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2016-ec-1
digital-circuits
semiconductor
mosfet
+
–
0
votes
0
answers
24
GATE ECE 2016 Set 1 | Question: 43
The functionality implemented by the circuit below is $2$-to-$1$ multiplexer $4$-to-$1$ multiplexer $7$-to-$1$ multiplexer $6$-to-$1$ multiplexer
The functionality implemented by the circuit below is$2$-to-$1$ multiplexer $4$-to-$1$ multiplexer$7$-to-$1$ multiplexer$6$-to-$1$ multiplexer
Milicevic3306
16.0k
points
252
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2016-ec-1
digital-circuits
combinational-circuits
multiplexers
decoders
+
–
0
votes
0
answers
25
GATE ECE 2016 Set 1 | Question: 44
In an $8085$ system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this? For POP, the data transceivers remain in the same direction as for instruction fetch ... in the stack pointer. Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order.
In an $8085$ system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?For POP, the data...
Milicevic3306
16.0k
points
100
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2016-ec-1
digital-circuits
microprocessor-8085
+
–
0
votes
0
answers
26
GATE ECE 2015 Set 3 | Question: 15
In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for logic $‘1’$. What logic gate does the circuit represent? $3$-input OR gate $3$-input NOR gate $3$-input AND gate $3$-input XOR gate
In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for...
Milicevic3306
16.0k
points
193
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2015-ec-3
digital-circuits
combinational-circuits
logic-gates
+
–
0
votes
0
answers
27
GATE ECE 2015 Set 3 | Question: 16
Which one of the following $8085$ microprocessor programs correctly calculates the product of two $8$-bit numbers stored in registers $B$ and $C?$ ...
Which one of the following $8085$ microprocessor programs correctly calculates the product of two $8$-bit numbers stored in registers $B$ and $C?$$\begin{array}{ll} {} & ...
Milicevic3306
16.0k
points
109
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-3
digital-circuits
microprocessor-8085
+
–
0
votes
0
answers
28
GATE ECE 2015 Set 3 | Question: 38
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing NOR gates to NAND gates inverters to buffers NOR gates to NAND gates and inverters to buffers $5\: V$ to ground
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the cir...
Milicevic3306
16.0k
points
194
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2015-ec-3
digital-circuits
sequential-circuit
flip-flops
+
–
0
votes
0
answers
29
GATE ECE 2015 Set 3 | Question: 49
Two sequences $x_{1}[n]$ and $x_{2}[n]$ have the same energy. Suppose $x_{1}[n]=\alpha\: 0.5 ^{n}\:u[n],$ where $\alpha$ is a positive real number and $u[n]$is the unit step sequence. Assume ݊$x_{2}[n]= \begin{cases} \sqrt{1.5}& \text{for } n = 0,1 \\ 0 &\text{otherwise.} \end{cases}$ Then the value of $\alpha$ is _________.
Two sequences $x_{1}[n]$ and $x_{2}[n]$ have the same energy. Suppose $x_{1}[n]=\alpha\: 0.5 ^{n}\:u[n],$ where $\alpha$ is a positive real number and $u[n]$is the unit s...
Milicevic3306
16.0k
points
84
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-3
numerical-answers
digital-circuits
+
–
1
votes
0
answers
30
GATE ECE 2015 Set 2 | Question: 14
In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively, NOR, OR OR, NAND NAND, OR AND,NAND
In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively,NOR, OROR, NANDNAND, ORAND,NA...
Milicevic3306
16.0k
points
161
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2015-ec-2
digital-circuits
combinational-circuits
logic-gates
+
–
0
votes
0
answers
31
GATE ECE 2015 Set 2 | Question: 15
In an $8085$ microprocessor, which one of the following instructions changes the content of the accumulator? MOV B, M PCHL RNZ SBI BEH
In an $8085$ microprocessor, which one of the following instructions changes the content of the accumulator?MOV B, MPCHLRNZSBI BEH
Milicevic3306
16.0k
points
135
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-2
digital-circuits
microprocessor-8085
+
–
0
votes
0
answers
32
GATE ECE 2015 Set 2 | Question: 16
A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.
A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.
Milicevic3306
16.0k
points
257
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2015-ec-2
numerical-answers
digital-circuits
sequential-circuit
counters
+
–
1
votes
0
answers
33
GATE ECE 2015 Set 2 | Question: 36
A function of Boolean variables $X, Y$ and $Z$ is expressed in terms of the min-terms as $F(X, Y, Z) = \Sigma (1, 2, 5, 6, 7)$ Which one of the product of sums given below is equal to the function $F(X, Y, Z)?$ ...
A function of Boolean variables $X, Y$ and $Z$ is expressed in terms of the min-terms as $$F(X, Y, Z) = \Sigma (1, 2, 5, 6, 7)$$Which one of the product of sums given bel...
Milicevic3306
16.0k
points
148
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-2
digital-circuits
boolean-algebra
+
–
0
votes
0
answers
34
GATE ECE 2015 Set 2 | Question: 37
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod-$2$ counter mod-$4$ counter mod-$5$ counter mod-$6$ counter
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod-$2$ counter mod-$4$ counter mod-$5$ counter mod-...
Milicevic3306
16.0k
points
231
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2015-ec-2
digital-circuits
sequential-circuit
counters
+
–
0
votes
0
answers
35
GATE ECE 2015 Set 2 | Question: 38
A $1$-to-$8$ demultiplexer with data input $D_{in}$ , address inputs $S_{0}, S_{1}, S_{2}$ (with $S_{0}$ as the LSB) and $\overline{Y_{0}}$ to $\overline{Y_{7}}$ as the eight demultiplexed outputs, is to be designed using two $2$-to-$4$ ... $D_{in}, S_{0}, S_{1}, S_{2} $ $D_{in}, S_{2}, S_{0}, S_{1}$
A $1$-to-$8$ demultiplexer with data input $D_{in}$ , address inputs $S_{0}, S_{1}, S_{2}$ (with $S_{0}$ as the LSB) and $\overline{Y_{0}}$ to $\overline{Y_{7}}$ as the e...
Milicevic3306
16.0k
points
172
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-2
digital-circuits
combinational-circuits
decoders
+
–
0
votes
0
answers
36
GATE ECE 2015 Set 1 | Question: 14
In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively B and F A and F H and F A and C
In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectivelyB and FA and FH and FA and C
Milicevic3306
16.0k
points
108
views
Milicevic3306
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Mar 27, 2018
Digital Circuits
gate2015-ec-1
digital-circuits
microprocessor-8085
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37
GATE ECE 2015 Set 1 | Question: 15
A $16$ Kb ($=16,384$ bits) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines needed for the row decoder is ___________
A $16$ Kb ($=16,384$ bits) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of addr...
Milicevic3306
16.0k
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130
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Milicevic3306
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Mar 27, 2018
Digital Circuits
gate2015-ec-1
numerical-answers
digital-circuits
decoders
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0
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0
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38
GATE ECE 2015 Set 1 | Question: 16
Consider a four bit $D$ to $A$ converter. The analog value corresponding to digital signals of values $0000$ and $0001$ are $0$ V and $0.0625$ V respectively. The analog value (in Volts) corresponding to the digital signal $1111$ is _________
Consider a four bit $D$ to $A$ converter. The analog value corresponding to digital signals of values $0000$ and $0001$ are $0$ V and $0.0625$ V respectively. The analog ...
Milicevic3306
16.0k
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127
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Milicevic3306
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Mar 27, 2018
Digital Circuits
gate2015-ec-1
numerical-answers
digital-circuits
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1
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0
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39
GATE ECE 2015 Set 1 | Question: 36
The Boolean expression $F(X,Y,Z) = \overline{X} \: Y \: \overline{Z}+ X \: \overline{Y} \: \overline{Z}+ X \: Y \: \overline{Z} + X \: Y \: Z$ ... $(X+\overline{Y}+\overline{Z})(\overline{X}+Y+Z)(\overline{X}+\overline{Y}+Z)(X + Y + Z)$
The Boolean expression $F(X,Y,Z) = \overline{X} \: Y \: \overline{Z}+ X \: \overline{Y} \: \overline{Z}+ X \: Y \: \overline{Z} + X \: Y \: Z$ converted into the canonica...
Milicevic3306
16.0k
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99
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Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-1
boolean-algebra
digital-circuits
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0
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0
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40
GATE ECE 2014 Set 4 | Question: 14
For a given sample-and-hold circuit, if the value of the hold capacitor is increased, then droop rate decreases and acquisition time decreases droop rate decreases and acquisition time increases droop rate increases and acquisition time decreases droop rate increases and acquisition time increases
For a given sample-and-hold circuit, if the value of the hold capacitor is increased, thendroop rate decreases and acquisition time decreasesdroop rate decreases and acqu...
Milicevic3306
16.0k
points
72
views
Milicevic3306
asked
Mar 26, 2018
Digital Circuits
gate2014-ec-4
digital-circuits
sample-and-hold-circuits
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