Questions without answers in Digital Circuits

A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared...

Give me the pyqs for number conversions

A $4$-bit weighted-resistor DAC with inputs $b_{3}, b_{2}, b_{1}$, and $b_{0}$ (MSB to LSB) is designed using an ideal opamp, as shown below. The switches are closed when...

A $10$-bit analog-to-digital converter (ADC) has a sampling frequency of $1\: \mathrm{MHz}$ and a full scale voltage of $3.3 \: \mathrm{V}$.For an input sinusoidal signal...

In the circuit shown below, the $\mathrm{AND}$ gate has a propagation delay of $1 \: \mathrm{ ns}$. The edge-triggered flip-flops have a set-up time of $2 \: \mathrm{ ns}...

As shown in the circuit, the initial voltage across the capacitor is $10 \mathrm{~V}$, with the switch being open. The switch is then closed at $t=0$. The total energy di...

​​​​​The sequence of states $\left(Q_{1} Q_{0}\right)$ of the given synchronous sequential circuit is - $\_\_\_\_\_\_\_$.$00 \rightarrow 10 \rightarrow 11 \rightarrow 00$...

​​​​​A full scale sinusoidal signal is applied to a $10$ -bit $\mathrm{ADC}$. The fundamental signal component in the $\mathrm{ADC}$ output has a normalized power of $1 \...

In the circuit shown below, the transistors $M_{1}$ and $M_{2}$ are biased in saturation. Their small signal transconductances are $g_{m 1}$ and $g_{m 2}$ respectively. N...

The synchronous sequential circuit shown below works at a clock frequency $1 \; \mathrm{GHz}$. The throughput, in $\text{Mbits/s,}$ and the latency, in $\text{ns,}$ respe...

The signal-to-noise ratio $\mathrm{SNR}$ of an $\mathrm{ADC}$ with a full-scale sinusoidal input is given to be $61.96 \mathrm{~dB}$. The resolution of the $\mathrm{ADC}$...

A sample and hold circuit is implemented using a resistive switch and a capacitor with a time constant of $1 \; \mu \mathrm{s}$. The time for the sampling switch to stay ...

Statement for Linked Answer Questions $81 a$ and $81 b$:Consider an $8085$ microprocessor systemIf in addition following code exists from $019 \mathrm{H}$ onwards,$\text{...

Statement for Linked Answer Questions 83a and 83bAsymmetric three-level midtread quantizer is to be designed assuming equiprobable occurence of all quantization levels.Th...

Each cell of a Static Random Access Memory contains$6 \; \text{MOS}$ transistors$4 \; \mathrm{MOS}$ transistors and $2$ capacitors$2 \; \text{MOS}$ transistors and $4$ ca...

A $2$ bit binary multiplier can be implemented using$2$ inputs $\text{ANDs}$ only$2$ input $\text{XOR s}$ and $4$ input $\text{AND}$ gates onlyTwo $2$ inputs $\text{NORs}...

In standard $\text{TTL}$, the 'totem pole' stage refers tothe multi-emitter input stagethe phase splitterthe output bufferopen collector output stage

The inverter $74 \; \mathrm{ALSO} 4$ has the following specifications\[ \begin{array}{l}\mathrm{I}_{\text {OH } \max }=-0.4 \mathrm{~mA}, \mathrm{l}_{\text {OLmax }}=8 \m...

The output of the logic gate in the figure is$0$$1$$\text{A}$$\mathrm{F}$

In an $8085 \; \mu \; \mathrm{P}$ system, the $\text{RST}$ instruction will cause an interruptonly if an interrupt service routine is not being executedonly if a bit in t...

The following insturctions have been executed by an $8085 \; \mu \mathrm{P}$$\begin{array}{cl}\text { ADDRESS (HEX) } & \text { INSTRUCTION } \\ 6010 & \text { LXI H, 8A ...

For the $\text{NMOS}$ logic gate shown in the figure is the logic function implemented is$\overline{\mathrm{ABCDE}}$$(\mathrm{AB}+\overline{\mathrm{C}}) \cdot(\overline{\...

The gate delay of an $\text{NMOS}$ inverter is dominated by charge time rather than discharge time becausethe driver transistor has larger threshold voltage than the load...

The boolean function $\mathrm{A}+\mathrm{BC}$ is a reduced form of$\mathrm{AB}+\mathrm{BC}$$(\mathrm{A}+\mathrm{B}) \cdot(\mathrm{A}+\mathrm{C})$$\overline{\mathrm{A}} \m...

(1) An $8$-bit wide $5$ word sequential memory will have$8$ Fixed $\text{‘AND'}$ gates and $4$ programmable $\text{‘OR'}$ gates(2) A $256 \times 4$ $\text{EFROM}$ hasEigh...

While moving data between registers of the $8085$ and the stack(1) a $\text{PUSH}$ instructionPre increments the stack pointer(2) a $\text{POP}$ instructionPost increment...

A sequence generator is shown in the figure. The counter status $\left(\mathrm{Q}_{0}, \mathrm{Q}_{1}, \mathrm{Q}_{2}\right)$ is initialised to $010$ using preset/clear i...

An $8085 \; \mu \mathrm{P}$ uses a $2 \; \mathrm{MHz}$ crystal. Find the time taken by it to execute the following delay subroutine, inclusive of the call instruction in ...

An $8$ bit successive approximation analog to digital converter has full scale reading of $2.55 \mathrm{~V}$ and its conversion time for an analog input of $1 \mathrm{~V}...

The number of hardware interrupts (which require an external signal to interrupt) present in an $8085$ microprocessor are$1$$4$$5$$13$