GATE ECE 2017 Set 2 | Question: 44

Question

Figure Ⅰ shows a $4$-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are $20$ ns, $15$ ns and $10$ ns, respectively. Assume all the inputs to the $4$-bit adder are initially reset to $0$.

 

Figure I

         

Figure II

At $t = 0$, the inputs to the $4$-bit adder are changed to $X_3X_2X_1X_0=1100$, $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The output of the ripple carry adder will be stable at $t$ (in ns) = ___________

Answer 1

for S₀₌2 EX-OR Gate Delay = 20*2 = 40 ns

Z₁₌1 EX-OR + 1 AND + 1 OR Gate Delay = 20 + 15 + 10 = 45 ns

for next 3 FA, the carry propagation delay will be = 1 AND + 1 OR Gate Delay = 15 + 10 = 25 ns

Time taken to stabilize the output = Total Propagation Delay = 45 + 25*3 = 120 ns 

Here i've also considered the time to stabilize for the final carry bit Z₄

Answer 2

Hope it helps