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For the logic circuit shown in the figure is the output $Y$ is equal to

1. $\overline{\mathrm{ABC}}$
2. $\overline{\mathrm{A}}+\overline{\mathrm{B}}+\overline{\mathrm{C}}$
3. $\overline{\mathrm{AB}}+\overline{\mathrm{BC}}+\overline{\mathrm{A}}+\overline{\mathrm{C}}$