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For the circuit shown in the following figure, $\mathrm{I}_{0}\text{-}\mathrm{I}_{3}$ are inputs to the $4: 1$ multiplexer. $\mathrm{R~(MSB)}$ and $\mathrm{S}$ are control bits.


The output $\text{Z}$ can be represented by

  1. $\text{PQ + P} \overline{\text{Q}} \text{S}+\overline{\text{Q}} \;\overline{\text{R}}\; \overline{\text{S}}$
  2. $\text{P} \overline{\text{Q}}+ \text{PQ} \overline{\text{R}}+\overline{\text{P}} \;\overline{\text{Q}}\; \overline{\text{S}}$
  3. $\text{P} \overline{\text{Q}} \;\overline{\text{R}}+\overline{\text{P}} \text{QR + PQRS}+\overline{\text{Q}}\; \overline{\text{R}} \;\overline{\text{S}}$
  4. $\text{PQ} \overline{\text{R}}+\text{PQR} \overline{\text{S}}+\text{P} \overline{\text{Q}}\; \overline{\text{R}} \text{S}+\overline{\text{Q}}\; \overline{\text{R}}\; \overline{\text{S}}$

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