Recent questions in Data Converters

A $4$-bit weighted-resistor DAC with inputs $b_{3}, b_{2}, b_{1}$, and $b_{0}$ (MSB to LSB) is designed using an ideal opamp, as shown below. The switches are closed when...

A $10$-bit analog-to-digital converter (ADC) has a sampling frequency of $1\: \mathrm{MHz}$ and a full scale voltage of $3.3 \: \mathrm{V}$.For an input sinusoidal signal...

​​​​​A full scale sinusoidal signal is applied to a $10$ -bit $\mathrm{ADC}$. The fundamental signal component in the $\mathrm{ADC}$ output has a normalized power of $1 \...

The signal-to-noise ratio $\mathrm{SNR}$ of an $\mathrm{ADC}$ with a full-scale sinusoidal input is given to be $61.96 \mathrm{~dB}$. The resolution of the $\mathrm{ADC}$...

A sample and hold circuit is implemented using a resistive switch and a capacitor with a time constant of $1 \; \mu \mathrm{s}$. The time for the sampling switch to stay ...

Statement for Linked Answer Questions 83a and 83bAsymmetric three-level midtread quantizer is to be designed assuming equiprobable occurence of all quantization levels.Th...

An $8$ bit successive approximation analog to digital converter has full scale reading of $2.55 \mathrm{~V}$ and its conversion time for an analog input of $1 \mathrm{~V}...

The number of comparators in a $4$ bit flash $\text{ADC}$ is$4$$5$$15$$16$

For the $4$ bit $\text{DAC}$ shown, the output voltage $v_{0}$ is$10 \mathrm{~V}$$5 \mathrm{~V}$$4 \mathrm{~V}$$8 \mathrm{~V}$

The resolution of a $4$ - bit counting $\text{ADC}$ is $0.5$ volts. For an analog input of $6.6$ volts, the digital output of the $\text{ADC}$ will be$1011$$1101$$1100$$1...

A monochrome video signal that ranges from $0$ to $8 \mathrm{~V}$, is digitized using an $8$-bit $\mathrm{ADC}$.Determine the resolution of the $\mathrm{ADC}$ in $\mathrm...

The number of comparators required in a $3$-bit comparator type ADC is$2$$3$$7$$8$

The advantage of using a dual slope $\text{ADC}$ in a digital voltmeter is thatits conversion time is smallits accuracy is highit gives output in $\text{BCD}$ formatit do...

The minimum number of comparators required to build an $8$ bit flash ADC is$8$$63$$255$$256$

A sinusoidal signal with peak-to-peak amplitude of $1.536 \mathrm{~V}$ is quantized into $128$ levels using a mid-rise uniform quantizer. The quantization-noise power is$...

Statement for Linked Answer Questions 83a and 83b:Asymmetric three-level midtread quantizer is to be designed assuming equiprobable occurence of all quantization levels.I...

If the number of bits per sample in a $\text{PCM}$ system is increased from improvement in signal-to quantisation noise ratio will be$3 \mathrm{~d B}$$6 \mathrm{~d B}$$2...

The signal to quantisation noise ratio in an $n$-bit $\text{PCM}$ systemdepends upon the sampling frequency employedis independent of the value of ' $n$ 'increases with i...

For an $\text{ADC}$, match the following(A) Flash converter(B) Dual slope converter(C) Successive approximation converterrequires a conversion time of the order of a few ...

A $12$ – bit $\text{ADC}$ is operating with a $1 \; \mu \; \mathrm{sec}$ clock period and the total conversion time is seen to be $14 \; \mu \;\mathrm{sec}$. The $\text{A...