in Others edited by
2 views
0 votes
0 votes

 

GATE ECE 2011 | Question-48

Common Data for Questions $48$ and $49:$

The channel resistance of an N-channel JFET shown in the figure below is $600 \; \Omega$ when the full channel thickness $\left(\mathrm{t}_{\mathrm{ch}}\right)$ of $10 \; \mu \mathrm{m}$ is available for conduction. The built-in voltage of the gate $\mathrm{P}^{+} \; \mathrm{N}$ junction $\left(\mathrm{V}_{\mathrm{b} i}\right)$ is $-1 \mathrm{~V}$. When the gate to source voltage $\left(\mathrm{V}_{\mathrm{GS}}\right)$ is $0 \mathrm{~V}$, the channel is depleted by $1 \; \mu \mathrm{m}$ on each side due to the built-in voltage and hence the thickness available for conduction is only $8 \; \mu \mathrm{m}$.

The channel resistance when $\mathrm{V}_{\mathrm{GS}}=0 \mathrm{~V}$ is

  1. $480 \; \Omega$
  2. $600 \; \Omega$
  3. $750 \; \Omega$
  4. $1000 \; \Omega$
in Others edited by
by
32.7k points
2 views

Please log in or register to answer this question.

Welcome to GO Electronics, where you can ask questions and receive answers from other members of the community.