in Digital Circuits edited by
58 views
0 votes
0 votes

A $1$-to-$8$ demultiplexer with data input $D_{in}$ , address inputs $S_{0}, S_{1}, S_{2}$ (with $S_{0}$ as the LSB) and $\overline{Y_{0}}$ to $\overline{Y_{7}}$ as the eight demultiplexed outputs, is to be designed using two $2$-to-$4$ decoders (with enable input $\overline{E}$ and address inputs $A_{0}$ and $A_{1}$) as shown in the figure. $D_{in} , S_{0}, S_{1}$ and $S_{2}$ are to be connected to $P, Q, R$ and $S,$ but not necessarily in this order. The respective input connections to $P, Q, R,$ and $S$ terminals should be

  1. $S_{2}, D_{in}, S_{0}, S_{1}$
  2. $S_{1}, D_{in}, S_{0}, S_{2} $
  3. $D_{in}, S_{0}, S_{1}, S_{2} $
  4. $D_{in}, S_{2}, S_{0}, S_{1}$
in Digital Circuits edited by
by
15.8k points
58 views

Please log in or register to answer this question.

Answer:
Ask
Welcome to GO Electronics, where you can ask questions and receive answers from other members of the community.