GATE ECE 2017 Set 1 | Question: 15

Question

In the latch circuit shown, the $NAND$ gates have non-zero, but unequal propagation delays. The present input condition is $P=Q=’0’$. If the input condition is changed simultaneously to $P=Q=’1’$, the outputs $X$ and $Y$ are,

• A. $X=’1’$, $Y=’1’$
• B. either $X=’1’$, $Y=’0’$ or $X=’0’$, $Y=’1’$
• C. either $X=’1’$, $Y=’1’$ or $X=’0’$, $Y=’0’$
• D. $X=’0’$, $Y=’0’$

Answer 1

Detailed Video Solution: https://youtu.be/hRUnJKDVQ4M?t=9077&feature=shared 

SR Latch Complete Lecture & ALL GATE CS-EC PYQs: https://youtu.be/hRUnJKDVQ4M 

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In $SR$ Latch with NAND gates:

When $S=0$ and $R=0,$ both outputs of the latch are equal to $1$, i.e., $Q_S=1$ and $Q_R=1$. 

Thus, the two outputs are no longer complements of each other. This is undesirable as many of the circuits that we build with these latches rely on the assumption that the two outputs are always complements of each other. 

• An even bigger problem occurs when we transition from $S=R=0$ to $S=R=1$: Oscillations and Uncertain States.

• When $S=R=0,$ we have $Q_S=Q_R=1$. After the transition to $S=R=1$, however, we get $Q_S=Q_R=0$, which would immediately cause $Q_S=Q_R=1$, and so on. If the gate delays are Same, then this oscillation will continue forever. 

• In practice, the oscillation dies down and the output settles into either $Q_S=1, Q_R=0$ or $Q_S=0, Q_R=1$. The problem is that we can't predict which one of these two it will settle into.

Detailed Video Solution: https://youtu.be/hRUnJKDVQ4M?t=9077&feature=shared 

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SR Latch Complete Lecture & ALL GATE CS-EC PYQs: https://youtu.be/hRUnJKDVQ4M