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Recent activity in Analog Circuits
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1
GATE ECE 2020 | Question: 18
In the circuit shown below, all the components are ideal. If $V_{i}$ is $+2\:V$, the current $I_{o}$ sourced by the op-amp is __________ $\text{mA}$.
In the circuit shown below, all the components are ideal. If $V_{i}$ is $+2\:V$, the current $I_{o}$ sourced by the op-amp is __________ $\text{mA}$.
shanmukh2099
140
points
279
views
shanmukh2099
answered
Mar 8, 2023
Analog Circuits
gate2020-ec
numerical-answers
op-amps
analog-circuits
+
–
0
votes
0
answers
2
GATE ECE 2015 Set 1 | Question: 42
In the circuit shown, $I_1=80$ mA and $I_2=4$ mA. Transistors $T_1$ and $T_2$ are identical. Assume that the thermal voltage $V_T$ is $26$ mV at $27^{\circ}C$. At $50^{\circ}C$, the value of the voltage $V_{12}=V_1 - V_2$ (in mV) is _______.
In the circuit shown, $I_1=80$ mA and $I_2=4$ mA. Transistors $T_1$ and $T_2$ are identical. Assume that the thermal voltage $V_T$ is $26$ mV at $27^{\circ}C$. At $50^{\c...
gatecse
1.6k
points
144
views
gatecse
recategorized
Nov 21, 2022
Diode Circuits
gate2015-ec-1
numerical-answers
+
–
0
votes
0
answers
3
GATE ECE 2018 | Question: 32
A $2\times 2$ ROM array is built with the help of diodes as shown in the circuit below. Here $W0$ and $W1$ are signals that select the word lines and $B0$ and $B1$ are signals that are output of the sense amps based on the stored data corresponding to the ... $\begin{bmatrix} 1 &0 \\ 1&0 \end{bmatrix}$ $\begin{bmatrix} 1 &1 \\ 0&0 \end{bmatrix}$
A $2\times 2$ ROM array is built with the help of diodes as shown in the circuit below. Here $W0$ and $W1$ are signals that select the word lines and $B0$ and $B1$ are si...
Lakshman Bhaiya
13.5k
points
248
views
Lakshman Bhaiya
retagged
Mar 2, 2021
Diode Circuits
gate2018-ec
digital-circuits
rom
+
–
0
votes
0
answers
4
GATE ECE 2016 Set 2 | Question: 6
In the circuit shown below, $V_{s}$ is a constant voltage source and $I_{L}$ is a constant current load. The value of $I_{L}$ that maximizes the power absorbed by the constant current load is $\frac{V_{S}}{4R} \\$ $\frac{V_{S}}{2R} \\$ $\frac{V_{S}}{R} \\$ $\infty$
In the circuit shown below, $V_{s}$ is a constant voltage source and $I_{L}$ is a constant current load. The value of $I_...
Lakshman Bhaiya
13.5k
points
160
views
Lakshman Bhaiya
recategorized
Mar 1, 2021
Analog Circuits
gate2016-ec-2
analog-circuits
+
–
0
votes
0
answers
5
GATE ECE 2015 Set 2 | Question: 8
The $2$-port admittance matrix of the circuit shown is given by $\begin{bmatrix}0.3 &0.2 \\0.2 &0.3 \end{bmatrix}$ $\begin{bmatrix} 15&5 \\5 &15 \end{bmatrix}$ $\begin{bmatrix} 3.33&5 \\5 &3.33 \end{bmatrix}$ $\begin{bmatrix} 0.3&0.4 \\0.4 &0.3 \end{bmatrix}$
The $2$-port admittance matrix of the circuit shown is given by$\begin{bmatrix}0.3 &0.2 \\0.2 &0.3 \end{bmatrix}$$\begin{bmatrix} 15&5 \\5 &15 \end{bmatrix}$$\begin{bmatr...
Lakshman Bhaiya
13.5k
points
82
views
Lakshman Bhaiya
retagged
Feb 27, 2021
Analog Circuits
gate2015-ec-2
analog-circuits
+
–
0
votes
0
answers
6
GATE ECE 2016 Set 1 | Question: 31
A network consisting of a finite number of linear resistor (R), inductor (L), and capacitor (C) elements, connected all in series or all in parallel, is excited with a source of the form ... $\sum_{k=1}^{3} a_k\cos(k\omega_0t+\phi_k) \\$ $\sum_{k=1}^{2} a_k\cos(k\omega_0t+\phi_k)$
A network consisting of a finite number of linear resistor (R), inductor (L), and capacitor (C) elements, connected all in series or all in parallel, is excited with a so...
soujanyareddy13
100
points
139
views
soujanyareddy13
recategorized
Nov 18, 2020
Analog Circuits
gate2016-ec-1
analog-circuits
impedance
+
–
0
votes
0
answers
7
GATE ECE 2014 Set 3 | Question: 14
An analog voltage in the range $0$ to $8$ V is divided in $16$ equal intervals for conversion to $4$-bit digital output. The maximum quantization error (in V) is __________
An analog voltage in the range $0$ to $8$ V is divided in $16$ equal intervals for conversion to $4$-bit digital output. The maximum quantization error (in V) is ________...
soujanyareddy13
100
points
192
views
soujanyareddy13
recategorized
Nov 18, 2020
Analog Circuits
gate2014-ec-3
numerical-answers
analog-circuits
voltage-reference-circuits
+
–
1
votes
0
answers
8
GATE ECE 2016 Set 3 | Question: 37
The injected excess electron concentration profile in the base region of an $npn$ BJT, biased in the active region, is linear, as shown in the figure. If the area of the emitter-base junction is $0.001\:cm^2 ,\mu_n=800cm^2/(V-s)$ in the ... is _________ (Given: thermal voltage $V_T=26 \: mV$ at room temperature, electronic charge $ q=1.6\times10^{-19}C$)
The injected excess electron concentration profile in the base region of an $npn$ BJT, biased in the active region, is linear, as shown in the figure. If the area of the ...
soujanyareddy13
100
points
242
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2016-ec-3
numerical-answers
analog-circuits
bipolar-junction-transistor
+
–
0
votes
0
answers
9
GATE ECE 2016 Set 2 | Question: 38
Consider a long-channel $NMOS$ transistor with source and body connected together. Assume that the electron mobility is independent of $V_{GS}$ and $V_{DS}.$ ... $and$ $g_{d}=\frac{\partial I_{D}}{\partial V_{DS}}$ The threshold voltage (in volts) of the transistor is _________
Consider a long-channel $NMOS$ transistor with source and body connected together. Assume that the electron mobility is independent of $V_{GS}$ and $V_{DS}.$ Given,$g_{m}...
soujanyareddy13
100
points
220
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2016-ec-2
numerical-answers
analog-circuits
nmos-transistor
+
–
0
votes
0
answers
10
GATE ECE 2016 Set 2 | Question: 12
A long-channel $NMOS$ transistor is biased in the linear region with $V_{DS}=50$ $m$ $V$ and is used as a resistance. Which one of the following statement is $NOT$ correct? If the device width $W$ is increased, the resistance ... decreases. If the device length $L$ is increased, the resistance increases. If $V_{GS}$ is incresed, the resistance increases.
A long-channel $NMOS$ transistor is biased in the linear region with $V_{DS}=50$ $m$ $V$ and is used as a resistance. Which one of the following statement is $NOT$ correc...
soujanyareddy13
100
points
139
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2016-ec-2
analog-circuits
nmos-transistor
+
–
1
votes
0
answers
11
GATE ECE 2015 Set 3 | Question: 34
The current in an enhancement mode NMOS transistor biased in saturation mode was measured to be $1\: mA$ at a drain-source voltage of $5\: V.$ When the drain-source voltage was increased to $6\: V$ while keeping gate-source voltage same, the ... the applied drain-source voltage. The channel length modulation parameter $\lambda\:(\text{in}\: V^{-1})$ is _______.
The current in an enhancement mode NMOS transistor biased in saturation mode was measured to be $1\: mA$ at a drain-source voltage of $5\: V.$ When the drain-source volta...
soujanyareddy13
100
points
121
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2015-ec-3
analog-circuits
nmos-transistor
+
–
0
votes
0
answers
12
GATE ECE 2014 Set 3 | Question: 38
Assuming that the Op-amp in the circuit shown is ideal, $V_{o}$ is given by $\frac{5}{2}V_{1}-3V_{2} \\$ $2V_{1}-\frac{5}{2}V_{2} \\$ $-\frac{3}{2}V_{1}+\frac{7}{2}V_{2} \\$ $-3V_{1}+\frac{11}{2}V_{2}$
Assuming that the Op-amp in the circuit shown is ideal, $V_{o}$ is given by $\frac{5}{2}V_{1}-3V_{2} \\$$2V_{1}-\frac{...
soujanyareddy13
100
points
106
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2014-ec-3
analog-circuits
op-amps
+
–
0
votes
0
answers
13
GATE ECE 2014 Set 3 | Question: 37
In the circuit shown, the silicon BJT has $\beta = 50$. Assume $V_{BE}= 0.7 \: V$ and $V_{CE(sat)}= 0.2 \: V$. Which one of the following statements is correct? For $R_{C}= 1$ $k$\Omega$, the BJT operates in the saturation region For $R_{ ... $k$\Omega$, the BJT operates in the cut-off region For $R_{C}= 20$ $k$\Omega$, the BJT operates in the linear region
In the circuit shown, the silicon BJT has $\beta = 50$. Assume $V_{BE}= 0.7 \: V$ and $V_{CE(sat)}= 0.2 \: V$. Which one of the following statements is correct? ...
soujanyareddy13
100
points
101
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2014-ec-3
bipolar-junction-transistor
analog-circuits
+
–
0
votes
0
answers
14
GATE ECE 2018 | Question: 43
In the circuit shown below, the $(W/L)$ value for $M_{2}$ is twice that for $M_{1}$. The two $\text{nMOS}$ transistors are otherwise identical. The threshold voltage $V_{T}$ for both transistors is $1.0\:V$. Note that $V_{GS}$ for $M_{2}$ ... $V_{x}$ is ________.
In the circuit shown below, the $(W/L)$ value for $M_{2}$ is twice that for $M_{1}$. The two $\text{nMOS}$ transistors are otherwise identical. The threshold voltage $V_{...
soujanyareddy13
100
points
129
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2018-ec
numerical-answers
analog-circuits
nmos-transistor
+
–
0
votes
0
answers
15
GATE ECE 2013 | Question: 4
In a forward biased $pn$ junction diode, the sequence of events that best describes the mechanism of current flow is injection, and subsequent diffusion and recombination of minority carriers injection, and subsequent drift and ... , and subsequent diffusion and generation of minority carriers extraction, and subsequent drift and recombination of minority carriers
In a forward biased $pn$ junction diode, the sequence of events that best describes the mechanism of current flow is injection, and subsequent diffusion and recombination...
soujanyareddy13
100
points
104
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2013-ec
analog-circuits
diodes
+
–
0
votes
0
answers
16
GATE ECE 2015 Set 1 | Question: 11
For the circuit with ideal diodes shown in the figure, the shape of the output $v_{\text{out}}$ for the given sine wave input $v_{\text{in}}$ will be
For the circuit with ideal diodes shown in the figure, the shape of the output $v_{\text{out}}$ for the given sine wave input $v_{\text{in}}$ will be
soujanyareddy13
100
points
114
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2015-ec-1
analog-circuits
diodes
+
–
0
votes
0
answers
17
GATE ECE 2014 Set 4 | Question: 39
For the common collector amplifier shown in the figure, the BJT has high $\beta$, negligible $V_{CE(sat)}$, and $V_{BE}=0.7 \: V$. The maximum undistorted peak-to-peak output voltage $v_o$ (in Volts) is __________
For the common collector amplifier shown in the figure, the BJT has high $\beta$, negligible $V_{CE(sat)}$, and $V_{BE}=0.7 \: V$. The maximum undistorted peak-to-peak ou...
soujanyareddy13
100
points
167
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2014-ec-4
numerical-answers
bjt-and-mosfet-amplifiers
analog-circuits
+
–
0
votes
0
answers
18
GATE ECE 2014 Set 4 | Question: 38
A BJT in a common-base configuration is used to amplify a signal received by a $50 \Omega$ antenna. Assume $kT/q=25 \: mV$. The value of the collector bias current (in mA) required to match the input impedance of the amplifier to the impedance of the antenna is __________.
A BJT in a common-base configuration is used to amplify a signal received by a $50 \Omega$ antenna. Assume $kT/q=25 \: mV$. The value of the collector bias current (in mA...
soujanyareddy13
100
points
102
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2014-ec-4
numerical-answers
bjt-and-mosfet-amplifiers
analog-circuits
+
–
0
votes
0
answers
19
GATE ECE 2020 | Question: 35
For the $\text{BJT}$ in the amplifier shown below, $V_{BE}=0.7V,\:kT/q=26\:mV$. Assume that $\text{BJT}$ output resistance $(r_{o})$ is very high and the base current is negligible. The capacitors are also assumed to be short circuited at signal frequencies. The ... The low frequency voltage gain $v_{o}/v_{i}$ of the amplifier is $-89.42$ $-128.21$ $-178.85$ $-256.42$
For the $\text{BJT}$ in the amplifier shown below, $V_{BE}=0.7V,\:kT/q=26\:mV$. Assume that $\text{BJT}$ output resistance $(r_{o})$ is very high and the base current is ...
soujanyareddy13
100
points
183
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2020-ec
analog-circuits
bipolar-junction-transistor
+
–
0
votes
0
answers
20
GATE ECE 2017 Set 2 | Question: 10
An $npn$ bipolar junction transistor (BJT) is operating in the active region. If the reverse bias across the base-collector junction is increased, then the effective base width increases and common-emitter current gain ... width decreases and common-emitter current gain increases the effective base width decreases and common-emitter current gain decreases
An $npn$ bipolar junction transistor (BJT) is operating in the active region. If the reverse bias across the base-collector junction is increased, then the effective base...
soujanyareddy13
100
points
142
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2017-ec-2
bipolar-junction-transistor
analog-circuits
+
–
0
votes
0
answers
21
GATE ECE 2015 Set 3 | Question: 35
An npn BJT having reverse saturation current $I_{S} = 10^{-15}\:A$ is biased in the forward active region with $V_{BE} = 700\: mV.$ The thermal voltage $(V_{T})$ is $25\: mV$ and the current gain $(β)$ may vary from $50$ to $150$ due to manufacturing variations. The maximum emitter current $(\text{in}\: \mu A)$ is ________.
An npn BJT having reverse saturation current $I_{S} = 10^{-15}\:A$ is biased in the forward active region with $V_{BE} = 700\: mV.$ The thermal voltage $(V_{T})$ is $25\:...
soujanyareddy13
100
points
196
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2015-ec-3
numerical-answers
bipolar-junction-transistor
analog-circuits
+
–
0
votes
0
answers
22
GATE ECE 2016 Set 2 | Question: 11
The Ebers-Moll model of a $BJT$ is valid only in active mode only in active and saturation modes only in active and cut-off modes in active, saturation and cut-off modes
The Ebers-Moll model of a $BJT$ is valid only in active modeonly in active and saturation modesonly in active and cut-off modesin active, saturation and cut-off modes
soujanyareddy13
100
points
111
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2016-ec-2
analog-circuits
bipolar-junction-transistor
+
–
0
votes
0
answers
23
GATE ECE 2014 Set 4 | Question: 35
Consider two BJTs biased at the same collector current with area $A_1=0.2 \mu m \times 0.2 \mu m$ and $A_2 = 300 \mu m \times 300 \mu m$. Assuming that all other device parameters are identical, $kT/q=26 \: mV$, the intrinsic carrier concentration ... $V_{BE1}-V_{BE2})$ is ________.
Consider two BJTs biased at the same collector current with area $A_1=0.2 \mu m \times 0.2 \mu m$ and $A_2 = 300 \mu m \times 300 \mu m$. Assuming that all other device p...
soujanyareddy13
100
points
135
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2014-ec-4
numerical-answers
analog-circuits
bipolar-junction-transistor
+
–
0
votes
0
answers
24
GATE ECE 2016 Set 2 | Question: 15
Which one of the following statements is correct about an ac-coupled common-emitter amplifier operating in the mid-band region? The device parasitic capacitances behave like open circuits, whereas coupling and bypass capacitances ... The device parasitic capacitances behave like short circuits, whereas coupling and bypass capacitances behave like open circuits.
Which one of the following statements is correct about an ac-coupled common-emitter amplifier operating in the mid-band region?The device parasitic capacitances behave li...
soujanyareddy13
100
points
164
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2016-ec-2
analog-circuits
amplifier
+
–
0
votes
0
answers
25
GATE ECE 2014 Set 4 | Question: 37
Consider the common-collector amplifier in the figure (bias circuitry ensures that the transistor operates in forward active region, but has been omitted for simplicity). Let $I_C$ be the collector current, $V_{BE}$ be the base-emitter voltage and $V_T$ be the ... of values of $R_E$? $g_mR_E <<1$ $I_CR_E>>V_T$ $g_mr_o>>1$ $V_{BE}>>V_T$
Consider the common-collector amplifier in the figure (bias circuitry ensures that the transistor operates in forward active region, but has been omitted for simplicity)....
soujanyareddy13
100
points
174
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2014-ec-4
analog-circuits
amplifier
+
–
0
votes
0
answers
26
GATE ECE 2015 Set 2 | Question: 39
The diode in the circuit given below has $V_{ON} = 0.7\:V$ but is ideal otherwise. The current $(\text{in}\: mA)$ in the $4\: k\Omega$ resistor is _______.
The diode in the circuit given below has $V_{ON} = 0.7\:V$ but is ideal otherwise. The current $(\text{in}\: mA)$ in the $4\: k\Omega$ resistor is _______.
soujanyareddy13
100
points
107
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2015-ec-2
numerical-answers
analog-circuits
diodes
+
–
0
votes
0
answers
27
GATE ECE 2017 Set 1 | Question: 15
A good transconductance amplifier should have high input resistance and low output resistance low input resistance and high output resistance high input and output resistances low input and output resistances
A good transconductance amplifier should havehigh input resistance and low output resistancelow input resistance and high output resistancehigh input and output resistanc...
soujanyareddy13
100
points
181
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2017-ec-1
analog-circuits
amplifier
+
–
0
votes
0
answers
28
GATE ECE 2016 Set 3 | Question: 41
In the circuit shown in the figure , the channel length modulation of all transistors is non-zero $(\lambda\neq0)$. Also, all transistors operate in saturation and have negligible body effect .The ac small signal voltage gain ($V_o/V_{in}$ ... $-g_{m1}(r_{o1}\mid\mid \left (\frac{1}{gm3}\mid\mid r_{o3})\mid\mid r_{o2} \right )$
In the circuit shown in the figure , the channel length modulation of all transistors is non-zero $(\lambda\neq0)$. Also, all transistors operate in saturation and have n...
soujanyareddy13
100
points
230
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2016-ec-3
analog-circuits
transistor
+
–
0
votes
0
answers
29
GATE ECE 2019 | Question: 40
In the circuits shown the threshold voltage of each $\text{nMOS}$ transistor is $0.6\:V.$ Ignoring the effect of channel length modulation and body bias. the values of $\text{Vout}1$ and $\text{Vout} 2,$ respectively, in volts, are $1.8$ and $1.2$ $2.4$ and $2.4$ $1.8$ and $2.4$ $2.4$ and $1.2$
In the circuits shown the threshold voltage of each $\text{nMOS}$ transistor is $0.6\:V.$ Ignoring the effect of channel length modulation and body bias. the values of $\...
soujanyareddy13
100
points
221
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2019-ec
analog-circuits
nmos-transistor
+
–
1
votes
0
answers
30
GATE ECE 2020 | Question: 33
The base of an $\text{npn BJT T1}$ has a linear doping profile $N_{B}\left ( x \right )$ as shown below. The base of another $\text{npn BJT T2}$ has a uniform doping $N_{B}$ of $10^{17}cm^{-3}$. All other parameters are identical for both the ... $\text{T1}$. approximately $2.5$ times that of $\text{T1}$. approximately $0.7$ times that of $\text{T1}$.
The base of an $\text{npn BJT T1}$ has a linear doping profile $N_{B}\left ( x \right )$ as shown below. The base of another $\text{npn BJT T2}$ has a uniform doping $N_...
soujanyareddy13
100
points
243
views
soujanyareddy13
recategorized
Nov 17, 2020
Analog Circuits
gate2020-ec
analog-circuits
bipolar-junction-transistor
+
–
0
votes
0
answers
31
GATE ECE 2014 Set 3 | Question: 11
The desirable characteristics of a transconductance amplifier are high input resistance and high output resistance high input resistance and low output resistance low input resistance and high output resistance low input resistance and low output resistance
The desirable characteristics of a transconductance amplifier are high input resistance and high output resistancehigh input resistance and low output resistancelow input...
soujanyareddy13
100
points
115
views
soujanyareddy13
edited
Nov 16, 2020
Analog Circuits
gate2014-ec-3
amplifier
analog-circuits
+
–
0
votes
0
answers
32
GATE ECE 2014 Set 3 | Question: 13
The figure shows a half-wave rectifier. The diode $D$ is ideal. The average steady-state current (in Amperes) through the diode is approximately ___________.
The figure shows a half-wave rectifier. The diode $D$ is ideal. The average steady-state current (in Amperes) through the diode is approximately ___________.
soujanyareddy13
100
points
369
views
soujanyareddy13
retagged
Nov 16, 2020
Analog Circuits
gate2014-ec-3
numerical-answers
analog-circuits
diodes
+
–
0
votes
0
answers
33
GATE ECE 2017 Set 1 | Question: 14
The Miller effect in the context of a Common Emitter amplifier explains An increase in the low-frequency cutoff frequency An increase in the high-frequency cutoff frequency A decrease in the low-frequency cutoff frequency A decrease in the high -frequency cutoff frequency
The Miller effect in the context of a Common Emitter amplifier explainsAn increase in the low-frequency cutoff frequencyAn increase in the high-frequency cutoff frequency...
soujanyareddy13
100
points
521
views
soujanyareddy13
retagged
Nov 16, 2020
Analog Circuits
gate2017-ec-1
amplifier
analog-circuits
+
–
0
votes
0
answers
34
GATE ECE 2016 Set 3 | Question: 15
In the astable multivibrator circuit shown in the figure, the frequency of oscillation (in kHz) at the output pin $3$ is _______
In the astable multivibrator circuit shown in the figure, the frequency of oscillation (in kHz) at the output pin $3$ is _______
soujanyareddy13
100
points
259
views
soujanyareddy13
retagged
Nov 16, 2020
Analog Circuits
gate2016-ec-3
numerical-answers
analog-circuits
oscillator
+
–
0
votes
0
answers
35
GATE ECE 2014 Set 2 | Question: 12
In the differential amplifier shown in the figure, the magnitude of the common-mode and differential-mode gains are $A_{CM}$ and $A_{d},$ respectively. If the resistance $R_{E}$ is increased, then $A_{cm}$ increases common-mode rejection ratio increases $A_{d}$ increases common-mode rejection ratio decreases
In the differential amplifier shown in the figure, the magnitude of the common-mode and differential-mode gains are $A_{CM}$ and $A_{d},$ respectively. If the resistance ...
soujanyareddy13
100
points
140
views
soujanyareddy13
edited
Nov 16, 2020
Analog Circuits
gate2014-ec-2
analog-circuits
amplifier
+
–
0
votes
0
answers
36
GATE ECE 2018 | Question: 37
A $dc$ current of $26\:\mu A$ flows through the circuit shown. The diode in the circuit is forward biased and it has an ideality factor of one. At the quiescent point, the diode has a junction capacitance of $0.5\:nF$. Its neutral region ... $\mu A$, correct to one decimal place) is __________.
A $dc$ current of $26\:\mu A$ flows through the circuit shown. The diode in the circuit is forward biased and it has an ideality factor of one. At the quiescent point, th...
soujanyareddy13
100
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Nov 16, 2020
Analog Circuits
gate2018-ec
numerical-answers
analog-circuits
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37
GATE ECE 2017 Set 1 | Question: 35
In the circuit shown, the voltage $V_{IN}(t)$ is described by: $V_{IN}(t)=\begin{cases} 0, & \text{for } t< 0 \\ 15 \text{Volts} & \text{for } t\geq 0 \end{cases}$ where $t$ is in seconds. The time (in seconds) at which the current $I$ in the circuit will reach the value $2$ Amperes is ___________.
In the circuit shown, the voltage $V_{IN}(t)$ is described by: $$V_{IN}(t)=\begin{cases} 0, & \text{for } t< 0 \\ 15 \text{Volts} & \text{for } t\geq 0 \end{cases}$$wher...
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Analog Circuits
gate2017-ec-1
numerical-answers
analog-circuits
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38
GATE ECE 2016 Set 3 | Question: 14
Consider the circuit shown in the figure. Assuming $V_{EE1} = V_{EE2} = 0.7$ volt, the value of the dc voltage $V_{C2}$(in volt) is _______
Consider the circuit shown in the figure. Assuming $V_{EE1} = V_{EE2} = 0.7$ volt, the value of the dc voltage $V_{C2}$(in volt) is _______
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Analog Circuits
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numerical-answers
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39
GATE ECE 2014 Set 1 | Question: 10
If fixed positive charges are present in the gate oxide of an $n$-channel enhancement type MOSFET, it will lead to a decrease in the threshold voltage channel length modulation an increase in substrate leakage current an increase in accumulation capacitance
If fixed positive charges are present in the gate oxide of an $n$-channel enhancement type MOSFET, it will lead to a decrease in the threshold voltagechannel length modul...
soujanyareddy13
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154
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soujanyareddy13
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Analog Circuits
gate2014-ec-1
analog-circuits
mosfet
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0
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40
GATE ECE 2014 Set 2 | Question: 9
An increase in the base recombination of a BJT will increase the common emitter dc current gain $\beta$ the breakdown voltage $BV_{CEO}$ the unity-gain cut-off frequency $f_{T}$ the transconductance $g_{m}$
An increase in the base recombination of a BJT will increasethe common emitter dc current gain $\beta$the breakdown voltage $BV_{CEO}$the unity-gain cut-off frequency $f_...
soujanyareddy13
100
points
140
views
soujanyareddy13
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Nov 16, 2020
Analog Circuits
gate2014-ec-2
analog-circuits
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