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81

GATE ECE 2012 | Question: 43
The state transition diagram for the logic circuit shown is

Milicevic3306 asked in Number Representations Mar 25, 2018

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82

GATE ECE 2012 | Question: 19
In the sum of products function $f(X,Y,Z)=\sum(2,3,4,5)$, the prime implicants are $\overline{X}Y,X\overline{Y}$ $\overline{X}Y,X\overline{Y}\overline{Z},X\overline{Y}Z$ $\overline{X}Y\overline{Z},\overline{X}YZ,X\overline{Y}$ $\overline{X}Y\overline{Z},\overline{X}YZ,X\overline{Y}\overline{Z},X\overline{Y}Z$

Milicevic3306 asked in Digital Circuits Mar 25, 2018

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83

GATE ECE 2012 | Question: 6
Consider the given circuit. In the circuit, the race around does not occur occurs when $\text{CLK}=0$ occurs when $\text{CLK}=1$ and $A=B=1$ occurs when $\text{CLK}=1$ and $A=B=0$

Milicevic3306 asked in Number Representations Mar 25, 2018

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84

GATE ECE 2012 | Question: 7
The output $Y$ of a $2-\text{bit}$ comparator is logic $1$ whenever the $2-\text{bit}$ input $A$ is greater than the $2-\text{bit}$ input $B$. The number of combinations for which the output is logic $1$, is $4$ $6$ $8$ $10$

Milicevic3306 asked in Digital Circuits Mar 25, 2018

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85

GATE ECE 2018 | Question: 46
In the circuit shown below, a positive edge-triggered $D$ Flip-Flop is used for sampling input data $D_{in}$ using clock $CK$. The XOR gate output $3.3$ volts for logic HIGH and $0$ volts for logic LOW levels. The data bit and clock periods are ... period is $0.3$, the average value (in volts, accurate to two decimal places) of the voltage at node $X$, is _________.

gatecse asked in Number Representations Feb 19, 2018

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86

GATE ECE 2018 | Question: 47
The logic gates shown in the digital circuit below use strong pull-down $\text{nMOS}$ transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes ... values of $X_{3}X_{2}X_{1}X_{0}$ (out of the $16$ possible values) that give $Y=1$ is ________.

gatecse asked in Number Representations Feb 19, 2018

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87

GATE ECE 2018 | Question: 45
A junction is made between $p^{-Si}$ with doping density $N_{A1}=10^{15}cm^{-3}$ and $p^{Si}$ with doping density $N_{A2}=10^{17}cm^{-3}.$ Given: Boltzmann constant $k=1.38\times 10^{-23}J\cdot K^{-1},$ electronic charge ... the magnitude of the built-in potential (in volts, correct to two decimal places) across this junction will be __________.

gatecse asked in Digital Circuits Feb 19, 2018

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88

GATE ECE 2018 | Question: 19
A traffic signal cycles from $\text{ GREEN to YELLOW, YELLOW to RED and RED to GREEN.}$ In each cycle, $\text{GREEN}$ is turned on for $70$ seconds,$\text{YELLOW}$ is turned on for $5$ seconds and the $\text{RED}$ is turned on $75$ ... $5$ second period. The minimum number of flip-flops required to implement this $\text{FSM}$ is _________.

gatecse asked in Digital Circuits Feb 19, 2018

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89

GATE ECE 2018 | Question: 8
The logic function $f(X, Y)$ realized by the given circuit is NOR AND NAND XOR

gatecse asked in Digital Circuits Feb 19, 2018

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90

GATE ECE 2018 | Question: 9
A function $F(A, B, C)$ defined by three Boolean variables $\text{A, B and C}$ when expressed as sum of products is given by $F=\overline{A}\:.\overline{B}\:.\overline{C}+\overline{A}\:.B\:.\overline{C}+A\:.\overline{B}\:.\overline{C}$ ...

gatecse asked in Digital Circuits Feb 19, 2018

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91

GATE ECE 2017 Set 2 | Question: 43
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is $S_0$. If the input sequence is $10101101001101$, starting with the left-most bit, then the number of times 'Out' will be $1$ is ____________

admin asked in Number Representations Nov 25, 2017

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92

GATE ECE 2017 Set 2 | Question: 15
For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is XNOR XOR NOR OR

admin asked in Number Representations Nov 23, 2017

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93

GATE ECE 2017 Set 2 | Question: 16
Consider the circuit shown in the figure. The Boolean expression $F$ implemented by the circuit is $\overline{X} \overline{Y} \overline{Z} + X Y +\overline{Y} Z $ $\overline{X} Y \overline{Z} + X Z + \overline{Y} Z $ $\overline{X} Y \overline{Z} +XY + \overline{Y} Z $ $\overline{X} \overline{Y} \overline{Z} + XZ+ \overline{Y}Z $

admin asked in Number Representations Nov 23, 2017

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94

GATE ECE 2017 Set 2 | Question: 17
In a DRAM, periodic refreshing is not required information is stored in a capacitor information is stored in a latch both read and write operations can be performed simultaneously

admin asked in Digital Circuits Nov 23, 2017

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95

GATE ECE 2017 Set 1 | Question: 44
A $4$-bit shift register circuit configured for right-shift operation, i.e. $D_{in}\rightarrow A,A\rightarrow B,B\rightarrow C,C\rightarrow D$, is shown. If the present state of the shift register is $ABCD=1101$, the number of clock cycles required to reach the state $ABCD=1111$ is _________.

admin asked in Number Representations Nov 17, 2017

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96

GATE ECE 2017 Set 1 | Question: 43
Which one of the following gives the simplified sum of products expression for the Boolean function $F=m_{0}+m_{2}+m_{3}+m_{5}$, where $m_{0},m_{2},m_{3}$ and $m_{5}$ are minterms corresponding to the inputs $A,B$ and $C$ with $A$ as the $MSB$ and ... $\overline{A} BC+\overline{A} \: \overline{C}+A \overline{B}C$

admin asked in Digital Circuits Nov 17, 2017

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97

GATE ECE 2017 Set 1 | Question: 45
The following FIVE instructions were executed on an $8085$ microprocessor. MVI A, $33$H MVI B, $78$H ADD B CMA ANI $32$H The Accumulator value immediately after the execution of the fifth instruction is $00H$ $10H$ $11H$ $32H$

admin asked in Digital Circuits Nov 17, 2017

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98

GATE ECE 2017 Set 1 | Question: 46
A finite state machine (FSM) is implemented using the D flip-flop A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are $Q_{A}Q_{B}=00,01,10$ and $11$. Assume that $X_{IN}$ is held at a constant logic ... states if $X_{IN}=0$ only two or four possible states if $X_{IN}=1$ only two or four possible states if $X_{IN}=0$

admin asked in Number Representations Nov 17, 2017

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99

GATE ECE 2017 Set 1 | Question: 15
In the latch circuit shown, the $NAND$ gates have non-zero, but unequal propagation delays. The present input condition is $P=Q=’0’$. If the input condition is changed simultaneously to $P=Q=’1’$, the outputs $X$ and $Y$ are, $X=’1’$, $Y=’1’$ either $X=’1’$, $Y=’0’$ or $X=’0’$, $Y=’1’$ either $X=’1’$, $Y=’1’$ or $X=’0’$, $Y=’0’$ $X=’0’$, $Y=’0’$

admin asked in Number Representations Nov 17, 2017

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100

GATE ECE 2017 Set 1 | Question: 17
Consider the D-Latch shown in the figure, which is transparent when its clock input $CK$ is high and has zero propagation delay. In the figure , the clock signal $CLK$ has a $50 \%$ duty cycle and $CLK2$ is a one-fifth period delayed version of $CLK1$.The duty cycle at the output of the latch in percentage is _________.

admin asked in Sequential Circuits Nov 17, 2017

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101

GATE ECE 2017 Set 1 | Question: 16
The clock frequency of an $8085$ microprocessor is $5$ MHz . If the time required to execute an instruction is $1.4 \: \mu s$, then the number of T-states needed for executing the instruction is $1$ $6$ $7$ $8$

admin asked in Digital Circuits Nov 17, 2017

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