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Recent questions tagged digital-circuits

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82
GATE ECE 2012 | Question: 43
The state transition diagram for the logic circuit shown is
The state transition diagram for the logic circuit shown is
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84
GATE ECE 2012 | Question: 6
Consider the given circuit. In the circuit, the race around does not occur occurs when $\text{CLK}=0$ occurs when $\text{CLK}=1$ and $A=B=1$ occurs when $\text{CLK}=1$ and $A=B=0$
Consider the given circuit.In the circuit, the race arounddoes not occuroccurs when $\text{CLK}=0$occurs when $\text{CLK}=1$ and $A=B=1$occurs when $\text{CLK}=1$ and $A=...
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85
GATE ECE 2012 | Question: 7
The output $Y$ of a $2-\text{bit}$ comparator is logic $1$ whenever the $2-\text{bit}$ input $A$ is greater than the $2-\text{bit}$ input $B$. The number of combinations for which the output is logic $1$, is $4$ $6$ $8$ $10$
The output $Y$ of a $2-\text{bit}$ comparator is logic $1$ whenever the $2-\text{bit}$ input $A$ is greater than the $2-\text{bit}$ input $B$. The number of combinations ...
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92
GATE ECE 2018 | Question: 9
A function $F(A, B, C)$ defined by three Boolean variables $\text{A, B and C}$ when expressed as sum of products is given by $F=\overline{A}\:.\overline{B}\:.\overline{C}+\overline{A}\:.B\:.\overline{C}+A\:.\overline{B}\:.\overline{C}$ ...
A function $F(A, B, C)$ defined by three Boolean variables $\text{A, B and C}$ when expressed as sum of products is given by$$F=\overline{A}\:.\overline{B}\:.\overline{C}...
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93
GATE ECE 2018 | Question: 8
The logic function $f(X, Y)$ realized by the given circuit is NOR AND NAND XOR
The logic function $f(X, Y)$ realized by the given circuit is NORANDNANDXOR
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98
GATE ECE 2017 Set 2 | Question: 15
For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is XNOR XOR NOR OR
For the circuit shown in the figure, P and Q are the inputs and Y is the output.The logic implemented by the circuit isXNOR XORNOROR
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99
GATE ECE 2017 Set 2 | Question: 17
In a DRAM, periodic refreshing is not required information is stored in a capacitor information is stored in a latch both read and write operations can be performed simultaneously
In a DRAM, periodic refreshing is not required information is stored in a capacitor information is stored in a latchboth read and write operations can be performed simult...
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102
GATE ECE 2017 Set 1 | Question: 45
The following FIVE instructions were executed on an $8085$ microprocessor. MVI A, $33$H MVI B, $78$H ADD B CMA ANI $32$H The Accumulator value immediately after the execution of the fifth instruction is $00H$ $10H$ $11H$ $32H$
The following FIVE instructions were executed on an $8085$ microprocessor.MVI A, $33$HMVI B, $78$HADD BCMAANI $32$HThe Accumulator value immediately after the execution o...
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106
GATE ECE 2017 Set 1 | Question: 16
The clock frequency of an $8085$ microprocessor is $5$ MHz . If the time required to execute an instruction is $1.4 \: \mu s$, then the number of T-states needed for executing the instruction is $1$ $6$ $7$ $8$
The clock frequency of an $8085$ microprocessor is $5$ MHz . If the time required to execute an instruction is $1.4 \: \mu s$, then the number of T-states needed for exec...
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