Recent questions in Combinational Circuits

The $K$-map for a Boolean function is shown in the figure is The number of essential prime implicants for this function is$4$$5$$6$$8$

The number of distinct Boolean expressions of $4$ variables is$16$$256$$1024$$65536$

The output of the $74$ series of $\text{TTL}$ gates is taken from a $\text{BJT}$ intotem pole and common collector configurationeither totem pole or open collector config...

Without any additional circuitry, an $8: 1 \; \mathrm{MUX}$ can be used to obtainsome but not all Boolean functions of $3$ variablesall functions of $3$ variables but non...

A $0$ to $6$ counter consists of $3$ flip flops and a combination circuit of $2$ input gate(s). The combination circuit consists ofone AND gateone OR gateone AND gate and...

The circuit shown in the figure has $4$ boxes each described by inputs $P, Q, R$ and outputs $Y, Z$ with\[\begin{array}{l}Y=P \oplus Q \oplus R \\Z=R Q+\bar{P} R+Q \bar{P...

If the functions $W, X, Y$ and $Z$ are as follows\[\begin{array}{l}W=R+\bar{P} Q+\bar{R} S \\X=P Q \bar{R} \bar{S}+\bar{P} \bar{Q} \bar{R} \bar{S}+P \bar{Q} \bar{R} \bar{...

The DTL, TTL, ECL and CMOS families of digital $\mathrm{IC}_{\mathrm{s}}$ are compared in the following $4$ columns$$\begin{array}{lllll} & \textbf{(P)} & \textbf{(Q)} & ...

The circuit shown in the figure convertsBCD to binary codeBinary to excess $-3$ codeExcess $-3$ to Gray codeGray to Binary code

In the circuit shown in the figure $\mathrm{A}$ is a parallel-in, parallel-out $4$ bit register, which loads at the rising edge of the clock $C$. The input lines are conn...

Choose the correct one from among the alternatives $\text{A, B, C, D}$ after matching an item from Group $1$ with the most appropriate item in Group $2.$$$\begin{array}{|...

Figure given below shows the internal schematic of a $\text{TTL AND-OR}$ -Invert $\text{(AOI)}$ gate. For the inputs shown in the given figure, the output $\text{Y}$ is $...

Given figure is the voltage transfer characteristic ofan NMOS inverter with enhancement mode transistor as loadan NMOS inverter with depletion mode transistor as loada CM...

The minimum number of $2$-to-$1$ multiplexers required to realize a $4$-to $1$ mulitiplexer is$1$$2$$3$$4$

The Boolean expression $\text{AC + B} \overline{\text{C}}$ is equivalent to$\overline{\mathrm{A}} \mathrm{C}+\mathrm{B} \overline{\mathrm{C}}+\mathrm{AC}$$\overline{\math...

A Boolean function $f$ of two variables $x$ and $y$ is defined as follows:\[f(0,0)=f(0,1)=f(1,1)=1 ; \quad f(1,0)=0\]Assuming complements of $x$ and $y$ are not available...

The Boolean function $f$ implemented in the figure using two input multiplexers is$\mathrm{A} \overline{\mathrm{B}} \text{C}+\mathrm{A} \overline{\mathrm{B}} \overline{\m...

The Boolean expression for the truth table shown is$$\begin{array}{|c|c|c|c|}\hline \mathrm{A} & \mathrm{B} & \mathrm{C} & \mathrm{F} \\\hline 0 & 0 & 0 & 0 \\\hline 0 & ...

The output of the circuit in the figure is equal to$0$$1$$\overline{\mathrm{A}} \mathrm{B}+\mathrm{A} \overline{\mathrm{B}}$$\overline{(\mathrm{A} * \mathrm{~B})} * \over...

The minimum number of $\text{NAND}$ gates required to implement the Boolean function $\mathrm{A}+\mathrm{A} \overline{\mathrm{B}}+\mathrm{A} \overline{\mathrm{B}} \mathrm...