Recent activity in Digital Circuits

Figure Ⅰ shows a $4$-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR g...

The given figure shows a ripple counter using positive edge triggered flip-flops. If the present state of the counter is $Q_{2}Q_{1}Q_{0}=011$, then its next state $\left...

A $3$-input majority gate is defined by the logic function $M(a,b,c)=ab+bc+ca$. Which one of the following gates is represented by the function $M(\overline{M(a,b,c)}, M(...

For the output $\text{F}$ to be $1$ in the logic circuit shown, the input combination should be$\mathrm{A}=1, \mathrm{~B}=1, \mathrm{C}=0$$\text{A = 1, B = 0, C = 0}$$\ma...

A binary ripple counter is designed to count $(0)_{10}$ to $(64)_{10}$.Which of the following is/are the number of flip-flops required to design the counter?$6$$7$$4$$5$

In a $\text{J-K}$ flip-flip we have $\text{J} = \overline{Q}$ and $\text{K}=1$. Assuming the flip-flop was initially cleared and then clocked for $6$ puleses, the sequenc...

The number of bytes required to represent the decimal number $1856357$ in packed BCD (Binary Coded Decimal) form is ___________.

In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively,NOR, OROR, NANDNAND, ORAND,NAND

In a given sequential circuit, initial states are $Q_1=1$ and $Q_2=0$. For a clock frequency of $1 \; \mathrm{MHz}$, the frequency of signal $\mathrm{Q}_2$ in $\mathrm{kH...

The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a square wave of $10$ cycles/second is applied to its clock (C) input.The...

The two numbers represented in signed $2\text{'s}$ complement form are $\mathrm{P}=11101101$ and $\mathrm{Q}=11100110$. If $\mathrm{Q}$ is subtracted from $\mathrm{P}$, t...

Two $2^{\prime}$ 's complement number having sign bits $x$ and $y$ are added and the sign bit of the result is $z$. Then, the occurrence of overflow is indicated by the B...

An equivalent $2^{\prime} s$ complement representation of the $2$'s complement number $1101$ is$110100$$001101$$110111$$111101$

In the circuit shown in the Figure, $A$ and $B$ are logic inputs and $Y$ is the logic output.Which of the following logic operations is realized by the circuit?NORORXORAN...

For the circuit shown below, the propagation delay of each $ \mathrm{NAND}$ gate is $1 \mathrm{~ns}$. The critical path delay, in $\text{ns,}$ is______________(rounded of...

The address of the first location of a $256$ kilo byte $(\mathrm{KB})$ memory is $(2500)_{\mathrm{H}}$.Choose the correct address of the last location of the memory.$(2 \...

​​​​​The propagation delay of the $2 \times 1$ MUX shown in the circuit is $10 \mathrm{~ns}$. Consider the propagation delay of the inverter as $0 \mathrm{~ns}$.If $\text...

Match the logic gates in Column A with their equivalents in Column B.$\text{P-2, Q-4, R-1, S-3}$$\text{P-4, Q-2, R-1, S-3}$$\text{P-2, Q-4, R-3, S-1}$$\text{P-4, Q-2, R-3...

A four-variable Boolean function is realized using $4\times 1$ multiplexers as shown in the figure.The minimized expression for $\text{F(U,V,W,X)}$ is $\left ( UV+\overli...

Consider the circuit shown in the figure. The Boolean expression $F$ implemented by the circuit is$\overline{X} \overline{Y} \overline{Z} + X Y +\overline{Y} Z $$\overlin...

Consider the multiplexer based logic circuit shown in the figure.Which one of the following Boolean functions is realized by the circuit?$F= W \overline{S_1} \: \overline...

In the circuit shown, $W$ and $Y$ are MSBs of the control inputs. The output $F$ is given by$F= W\overline{X}+\overline{W}X+\overline{Y}\overline{Z}$$F= W\overline{X}+\ov...