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Recent activity in Sequential Circuits

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GATE ECE 2005 | Question: 57
The given figure shows a ripple counter using positive edge triggered flip-flops. If the present state of the counter is $Q_{2}Q_{1}Q_{0}=011$, then its next state $\left...
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504
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GATE ECE 1996 | Question 1.11
A pulse train can be delayed by a finite number of clock periods usinga serial-in serial-out shift registera serial-in parallel-out shift registera parallel-in serial-out...
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331
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GATE ECE 1998 | Question 2.11
The figure shows a mod-$\mathrm{K}$ counter, here $\mathrm{K}$ is equal to$1$$2$$3$$4$
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395
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GATE ECE 1997 | Question 14
A sequence generator is shown in the figure. The counter status $\left(\mathrm{Q}_{0}, \mathrm{Q}_{1}, \mathrm{Q}_{2}\right)$ is initialised to $010$ using preset/clear i...
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GATE ECE 1997 | Question 4.8
In a $\text{J-K}$ flip-flip we have $\text{J} = \overline{Q}$ and $\text{K}=1$. Assuming the flip-flop was initially cleared and then clocked for $6$ puleses, the sequenc...
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GATE ECE 1991 | Question 1.29
An $\text{S-R FLIP-FLOP}$ can be converted into a $\textsf{T FLIP FLOP}$ by connecting __________ to $\mathrm{Q}$ and ___________ to $\mathrm{\overline{Q}}$.
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GATE ECE 1999 | Question 2.12
The ripple counter shown in the given figure works as a$\bmod -3$ up counter$\bmod -5$ up counter$\bmod - 3$ down counter$\bmod - 5$ down counter
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GATE ECE 2012 | Question: 43
The state transition diagram for the logic circuit shown is
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GATE ECE 2023 | Question: 53
In a given sequential circuit, initial states are $Q_1=1$ and $Q_2=0$. For a clock frequency of $1 \; \mathrm{MHz}$, the frequency of signal $\mathrm{Q}_2$ in $\mathrm{kH...
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GATE ECE 2024 | Question: 32
​​​​​The sequence of states $\left(Q_{1} Q_{0}\right)$ of the given synchronous sequential circuit is - $\_\_\_\_\_\_\_$.$00 \rightarrow 10 \rightarrow 11 \rightarrow 00$...
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GATE ECE 2026 | Question: 25
The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a square wave of $10$ cycles/second is applied to its clock (C) input.The...
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1 1 answer
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GATE ECE 2025 | Question: 35
A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input $P 0$ is set to logic '$0$ ' and $P 1$ is set to logic '...
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GATE ECE 1994 | Question 2.15
Synchronous counters are __________ than the ripple counters.
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GATE ECE 2001 | Question: 1.12
For the ring oscillator shown in the figure, the propagation delay of each inverter is $100$ pico sec. What is the fundamental frequency of the oscillator output?$10 \; \...
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553
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GATE ECE 2025 | Question: 52
In the circuit shown below, the $\mathrm{AND}$ gate has a propagation delay of $1 \: \mathrm{ ns}$. The edge-triggered flip-flops have a set-up time of $2 \: \mathrm{ ns}...
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GATE ECE 2023 | Question: 14
The synchronous sequential circuit shown below works at a clock frequency $1 \; \mathrm{GHz}$. The throughput, in $\text{Mbits/s,}$ and the latency, in $\text{ns,}$ respe...
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GATE ECE 2009 | Question: 39
What are the counting states $\left(Q_{1}, Q_{2}\right)$ for the counter shown in the figure below?$11,10,00,11,10, \ldots$$01,10,11,00,01, \ldots$$00,11,01,10,00, \ldots...
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GATE ECE 2008 | Question: 59
For each of the positive edge-triggered $\text{J-K}$ flip flop used in the following figure, the propagation delay is $\Delta T$.Which of the following waveforms correctl...
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GATE ECE 2008 | Question: 60
For the circuit shown in the figure, $\mathrm{D}$ has a transition from $0$ to $1$ after $\text{CLK}$ changes from $1$ to $0 .$ Assume gate delays to be negligible.Which ...
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2 answers 2 answers
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GATE ECE 2007 | Question: 44
The following binary values were applied to the $\mathrm{X}$ and $\mathrm{Y}$ inputs of the NAND latch shown in the figure in the sequence indicated below:\[ \mathrm{X}=0...
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GATE ECE 2007 | Question: 45
For the circuit shown, the counter state $\left(\mathrm{Q}_{1} \mathrm{Q}_{0}\right)$ follows the sequence$00,01,10,11,00 \ldots$$00,01,10,00,01 \ldots$$00,01,11,00,01 \l...
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1 1 vote
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GATE ECE 2006 | Question: 47
Two $\text{D}$-flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following $\mathrm{Q}_{1} \mathrm{Q}_{0}$ sequence $00 \long...
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GATE ECE 2005 | Question: 56
The present output $Q_{n}$ of an edge triggered JK flip-flop is logic $0.$ If $\mathrm{J}=1$, then $\mathrm{Q}_{n+1}$cannot be determinedwill be logic $0$will be logic $1...
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GATE ECE 2004 | Question: 13
A master-slave flip-flop has the characteristic thatchange in the input immediately reflected in the outputchange in the output occurs when the state of the master is aff...
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GATE ECE 2004 | Question: 56
In the modulo-$6$ ripple counter shown in the given figure, the output of the $2$-input gate is used to clear the J-K flip-flops.The $2$-input gate isa NAND gatea NOR gat...
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GATE ECE 2003 | Question: 55
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip flops having a propagation delay of $10 \mathrm{~ns}$ each. If the worst case delay in the ...
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GATE ECE 2000 | Question 2.9
A sequential circuit using $D$ Flip-Flop and logic gates is shown in figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is$S-R$ Flip-Flop with in...
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GATE ECE 2000 | Question 2.11
In given figure, the $J$ and $K$ inputs of all the four Flip-Flips are made high. The frequency of the signal at output $Y$ is$0.833 \; \mathrm{kHz}$$1.0 \; \mathrm{kHz}$...
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GATE ECE 1999 | Question 11
The circuit diagram of a synchronous counter is shown in the given figure. Determine the sequence of states of the counter assuming that the initial state is '$000$'. Giv...
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GATE ECE 1998 | Question 15
The $\text{mod}-5$ counter shown in the figure is counts through states $Q_{2} Q_{1} Q_{0}=000,001,010,011$ and $100$(a) Will the counter lockout if it happen to be in an...
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