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GATE ECE 2020 | Question: 50
For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{\text{setup}}$ is the setup-time, and $t_{\text{hold}}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is _________$\text{MHz}$.
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2
GATE ECE 2018 | Question: 31
A four-variable Boolean function is realized using $4\times 1$ multiplexers as shown in the figure. The minimized expression for $\text{F(U,V,W,X)}$ is $\left ( UV+\overline{U}\:\overline{V}\right )\overline{W}$ ... $\left ( U\:\overline{V}+\overline{U}\:V\right )\left (\overline{W}\: \overline{X}+\overline{W}\:X\right )$
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3
GATE ECE 2017 Set 2 | Question: 44
Figure Ⅰ shows a $4$-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are $20$ ns, $15$ ns and $10$ ns, respectively. Assume ... $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The output of the ripple carry adder will be stable at $t$ (in ns) = ___________
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4
GATE ECE 2020 | Question: 32
The band diagram of a $p$-type semiconductor with a band-gap of $1$ eV is shown. Using this semiconductor, a $\text{MOS}$ capacitor having $V_{TH}$ of $-0.16 V$, ${C}'_{ox}$ of $100\:nF/cm^{2}$ and a metal work function of $3.87 \: eV$ is fabricated. There is no charge ... $1.70\times 10^{-8}$ $0.52\times 10^{-8}$ $1.41\times 10^{-8}$ $0.93\times 10^{-8}$
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GATE ECE 2016 Set 3 | Question: 10
The $I-V$ characteristics of three types of diodes at the room temperature, made of semiconductors $X, Y$ and $Z$, are shown in the figure. Assume that the diodes are uniformly doped and identical in all respects except their materials. If $E_{gX}$,$E_{gY}$ ... $E_{gX}=E_{gY}=E_{gZ}$ $E_{gX}<E_{gY}<E_{gZ}$ no relationship among these band gaps exists.
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GATE ECE 2016 Set 3 | Question: 17
The logic functionality realized by the circuit shown below is $OR$ $XOR$ $NAND$ $AND$
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7
GATE ECE 2016 Set 3 | Question: 44
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2$ ns, $1.5$ ns and $1$ ns, respectively. If all the inputs $P, Q, R, S$ and $T$ are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is _________
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8
GATE ECE 2016 Set 3 | Question: 45
For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a $\text{mod}-5\:\text{counter}$ $\text{mod}-6\:\text{counter}$ $\text{mod}-7\:\text{counter}$ $\text{mod}-8\:\text{counter}$
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9
GATE ECE 2016 Set 2 | Question: 17
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flip-flops $D_{1} \:, D_{2} \:, D_{3} \:, D_{4}$ and $D_{5}$ are initialized with ... $0$, respectively. The clocks has a $30\%$ duty cycle. The average power dissipated (in $mW$) in the resistor $R$ is _________
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10
GATE ECE 2016 Set 2 | Question: 18
A $4:1$ multiplexer is to be used for generating the output carry of a full adder. $A$ and $B$ are the bits to be added while $C_{in}$ is the input carry and $C_{out}$ is the output carry. $A$ and $B$ are to be used as the select bits with $A$ being the more significant select ... $I_{3}=C_{in}$ $I_{0}=0, I_{1}=C_{in},I_{2}=1$ and $I_{3}=C_{in}$
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GATE ECE 2016 Set 2 | Question: 43
In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source $V_{in}$ ... maximum sampling rate? $1$ megasamples per second $6$ megasamples per second $64$ megasamples per second $256$ megasamples per second
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12
GATE ECE 2016 Set 1 | Question: 11
A small percentage of impurity is added to an intrinsic semiconductor at $300 \: K$. Which one of the following statements is true for the energy band diagram shown in the following figure? Intrinsic semiconductor doped with pentavalent ... atoms to form $p$-type semiconductor. Intrinsic semiconductor doped with trivalent atoms to form $p$-type semiconductor.
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13
GATE ECE 2015 Set 3 | Question: 15
In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for logic $‘1’$. What logic gate does the circuit represent? $3$-input OR gate $3$-input NOR gate $3$-input AND gate $3$-input XOR gate
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14
GATE ECE 2015 Set 3 | Question: 37
A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown. Which one of the following statements is TRUE? Gate $1$ is a universal gate Gate $2$ is a universal gate Gate $3$ is a universal gate None of the gates shown is a universal gate
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15
GATE ECE 2015 Set 3 | Question: 38
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing NOR gates to NAND gates inverters to buffers NOR gates to NAND gates and inverters to buffers $5\: V$ to ground
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16
GATE ECE 2015 Set 2 | Question: 14
In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively, NOR, OR OR, NAND NAND, OR AND,NAND
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17
GATE ECE 2015 Set 2 | Question: 16
A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.
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18
GATE ECE 2015 Set 2 | Question: 37
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod-$2$ counter mod-$4$ counter mod-$5$ counter mod-$6$ counter
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19
GATE ECE 2014 Set 4 | Question: 36
An N-type semiconductor having uniform doping is biased as shown in the figure. If $E_C$ is the lowest energy level of the conduction band, $E_V$ is the highest energy level of the valance band and $E_F$ is the Fermi level, which one of the following represents the energy band diagram for the biased N-type semiconductor?
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20
GATE ECE 2014 Set 4 | Question: 40
An $8$- to $1$ multiplexer is used to implement a logical function $Y$ as shown in the figure. The output $Y$ is given by $Y = A \: \overline{B} \:C+A \: \overline{C} \:D$ $Y = \overline{A} \: B \:C +A \: \overline{B} \: D$ $Y = A \: B \: \overline{C} + \overline{A} \: C \:D$ $Y= \overline{A} \: \overline{B} \: D + A \: \overline{B} \: C$
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21
GATE ECE 2014 Set 3 | Question: 15
The circuit shown in the figure is a Toggle Flip Flop JK Flip Flop SR Latch Master-Slave D Flip Flop
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22
GATE ECE 2014 Set 3 | Question: 16
Consider the multiplexer based logic circuit shown in the figure. Which one of the following Boolean functions is realized by the circuit? $F= W \overline{S_1} \: \overline{S_2}$ $F= WS_1+WS_2 + S_{1}S_{2}$ $F= \overline{W}+S_{1}+S_{2}$ $F= W\oplus S_{1}\oplus S_{2}$
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GATE ECE 2014 Set 3 | Question: 41
In the circuit shown, $W$ and $Y$ are MSBs of the control inputs. The output $F$ is given by $F= W\overline{X}+\overline{W}X+\overline{Y}\overline{Z}$ $F= W\overline{X}+\overline{W}X+\overline{Y}Z$ $F= W\overline{X}\overline{Y}+\overline{W}X\overline{Y}$ $F= ( \overline{W}+\overline{X} )\overline{Y}\overline{Z}$
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GATE ECE 2014 Set 3 | Question: 42
If $X$ and $Y$ are inputs and the Difference $(D=X-Y)$ and the Borrow $(B)$ are the outputs, which one of the following diagrams implements a half-subtractor?
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25
GATE ECE 2014 Set 3 | Question: 54
A region shown below contains a perfect conducting half-space and air. The surface current $\overrightarrow{K_{s}}$ on the surface of the perfect conductor is $\overrightarrow{K_{s}}= \hat{x}2$ amperes per meter. The tangential $\overrightarrow{H}$ field in the ... per meter $\hat{x}2$ amperes per meter $-\hat{z}2$ amperes per meter $\hat{z}2$ amperes per meter
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GATE ECE 2014 Set 1 | Question: 16
Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of $1\: MHz$ are applied as shown. The frequency $(\text{in}\:kHz)$ of the waveform at $Q3$ is ________.
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27
GATE ECE 2014 Set 1 | Question: 42
The digital logic shown in the figure satisfies the given state diagram when $Q1$ is connected to input $A$ of the XOR gate. Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram? Input $A$ is ... $A$ is connected to $\overline{Q1}$ and $S$ is complemented Input $A$ is connected to $\overline{Q1}$
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GATE ECE 2012 | Question: 43
The state transition diagram for the logic circuit shown is
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29
GATE ECE 2012 | Question: 6
Consider the given circuit. In the circuit, the race around does not occur occurs when $\text{CLK}=0$ occurs when $\text{CLK}=1$ and $A=B=1$ occurs when $\text{CLK}=1$ and $A=B=0$
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30
GATE ECE 2018 | Question: 47
The logic gates shown in the digital circuit below use strong pull-down $\text{nMOS}$ transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes ... values of $X_{3}X_{2}X_{1}X_{0}$ (out of the $16$ possible values) that give $Y=1$ is ________.
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31
GATE ECE 2018 | Question: 46
In the circuit shown below, a positive edge-triggered $D$ Flip-Flop is used for sampling input data $D_{in}$ using clock $CK$. The XOR gate output $3.3$ volts for logic HIGH and $0$ volts for logic LOW levels. The data bit and clock periods are ... period is $0.3$, the average value (in volts, accurate to two decimal places) of the voltage at node $X$, is _________.
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32
GATE ECE 2017 Set 2 | Question: 43
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is $S_0$. If the input sequence is $10101101001101$, starting with the left-most bit, then the number of times 'Out' will be $1$ is ____________
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GATE ECE 2017 Set 2 | Question: 16
Consider the circuit shown in the figure. The Boolean expression $F$ implemented by the circuit is $\overline{X} \overline{Y} \overline{Z} + X Y +\overline{Y} Z $ $\overline{X} Y \overline{Z} + X Z + \overline{Y} Z $ $\overline{X} Y \overline{Z} +XY + \overline{Y} Z $ $\overline{X} \overline{Y} \overline{Z} + XZ+ \overline{Y}Z $
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34
GATE ECE 2017 Set 2 | Question: 15
For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is XNOR XOR NOR OR
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35
GATE ECE 2017 Set 1 | Question: 46
A finite state machine (FSM) is implemented using the D flip-flop A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are $Q_{A}Q_{B}=00,01,10$ and $11$. Assume that $X_{IN}$ is held at a constant logic ... states if $X_{IN}=0$ only two or four possible states if $X_{IN}=1$ only two or four possible states if $X_{IN}=0$
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36
GATE ECE 2017 Set 1 | Question: 44
A $4$-bit shift register circuit configured for right-shift operation, i.e. $D_{in}\rightarrow A,A\rightarrow B,B\rightarrow C,C\rightarrow D$, is shown. If the present state of the shift register is $ABCD=1101$, the number of clock cycles required to reach the state $ABCD=1111$ is _________.
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37
GATE ECE 2017 Set 1 | Question: 15
In the latch circuit shown, the $NAND$ gates have non-zero, but unequal propagation delays. The present input condition is $P=Q=’0’$. If the input condition is changed simultaneously to $P=Q=’1’$, the outputs $X$ and $Y$ are, $X=’1’$, $Y=’1’$ either $X=’1’$, $Y=’0’$ or $X=’0’$, $Y=’1’$ either $X=’1’$, $Y=’1’$ or $X=’0’$, $Y=’0’$ $X=’0’$, $Y=’0’$
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