Recent activity by gatecse / GO Electronics

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1

GATE ECE 2016 Set 3 | Question: 10
The $I-V$ characteristics of three types of diodes at the room temperature, made of semiconductors $X, Y$ and $Z$, are shown in the figure. Assume that the diodes are uniformly doped and identical in all respects except their materials. If $E_{gX}$,$E_{gY}$ ... $E_{gX}=E_{gY}=E_{gZ}$ $E_{gX}<E_{gY}<E_{gZ}$ no relationship among these band gaps exists.

The $I-V$ characteristics of three types of diodes at the room temperature, made of semiconductors $X, Y$ and $Z$, are shown in the figure. Assume that the diodes are uni...

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edited Nov 27, 2022

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GATE ECE 2020 | Question: 32
The band diagram of a $p$-type semiconductor with a band-gap of $1$ eV is shown. Using this semiconductor, a $\text{MOS}$ capacitor having $V_{TH}$ of $-0.16 V$, ${C}'_{ox}$ of $100\:nF/cm^{2}$ and a metal work function of $3.87 \: eV$ is fabricated. There is no ... $1.70\times 10^{-8}$ $0.52\times 10^{-8}$ $1.41\times 10^{-8}$ $0.93\times 10^{-8}$

The band diagram of a $p$-type semiconductor with a band-gap of $1$ eV is shown. Using this semiconductor, a $\text{MOS}$ capacitor having $V_{TH}$ of $-0.16 V$, ${C}'_{o...

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edited Nov 27, 2022

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GATE ECE 2017 Set 1 | Question: 44
A $4$-bit shift register circuit configured for right-shift operation, i.e. $D_{in}\rightarrow A,A\rightarrow B,B\rightarrow C,C\rightarrow D$, is shown. If the present state of the shift register is $ABCD=1101$, the number of clock cycles required to reach the state $ABCD=1111$ is _________.

A $4$-bit shift register circuit configured for right-shift operation, i.e. $D_{in}\rightarrow A,A\rightarrow B,B\rightarrow C,C\rightarrow D$, is shown. If the present s...

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edited Nov 27, 2022

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GATE ECE 2016 Set 1 | Question: 11
A small percentage of impurity is added to an intrinsic semiconductor at $300 \: K$. Which one of the following statements is true for the energy band diagram shown in the following figure? Intrinsic semiconductor doped with pentavalent ... atoms to form $p$-type semiconductor. Intrinsic semiconductor doped with trivalent atoms to form $p$-type semiconductor.

A small percentage of impurity is added to an intrinsic semiconductor at $300 \: K$. Which one of the following statements is true for the energy band diagram shown in th...

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edited Nov 27, 2022

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GATE ECE 2014 Set 4 | Question: 36
An N-type semiconductor having uniform doping is biased as shown in the figure. If $E_C$ is the lowest energy level of the conduction band, $E_V$ is the highest energy level of the valance band and $E_F$ is the Fermi level, which one of the following represents the energy band diagram for the biased N-type semiconductor?

An N-type semiconductor having uniform doping is biased as shown in the figure.If $E_C$ is the lowest energy level of the conduction band, $E_V$ is the highest energy lev...

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edited Nov 27, 2022

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GATE ECE 2017 Set 1 | Question: 15
In the latch circuit shown, the $NAND$ gates have non-zero, but unequal propagation delays. The present input condition is $P=Q=’0’$. If the input condition is changed simultaneously to $P=Q=’1’$, the outputs $X$ and $Y$ are, $X=’1’$, $Y=’1’$ either $X=’1’$, $Y=’0’$ or $X=’0’$, $Y=’1’$ either $X=’1’$, $Y=’1’$ or $X=’0’$, $Y=’0’$ $X=’0’$, $Y=’0’$

In the latch circuit shown, the $NAND$ gates have non-zero, but unequal propagation delays. The present input condition is $P=Q=’0’$. If the input condition is change...

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recategorized Nov 27, 2022

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GATE ECE 2016 Set 2 | Question: 18
A $4:1$ multiplexer is to be used for generating the output carry of a full adder. $A$ and $B$ are the bits to be added while $C_{in}$ is the input carry and $C_{out}$ is the output carry. $A$ and $B$ are to be used as the select bits with $A$ being the more significant select ... $I_{3}=C_{in}$ $I_{0}=0, I_{1}=C_{in},I_{2}=1$ and $I_{3}=C_{in}$

A $4:1$ multiplexer is to be used for generating the output carry of a full adder. $A$ and $B$ are the bits to be added while $C_{in}$ is the input carry and $C_{out}$ is...

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edited Nov 27, 2022

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GATE ECE 2014 Set 4 | Question: 40
An $8$- to $1$ multiplexer is used to implement a logical function $Y$ as shown in the figure. The output $Y$ is given by $Y = A \: \overline{B} \:C+A \: \overline{C} \:D$ $Y = \overline{A} \: B \:C +A \: \overline{B} \: D$ $Y = A \: B \: \overline{C} + \overline{A} \: C \:D$ $Y= \overline{A} \: \overline{B} \: D + A \: \overline{B} \: C$

An $8$- to $1$ multiplexer is used to implement a logical function $Y$ as shown in the figure. The output $Y$ is given by$Y = A \: \overline{B} \:C+A \: \overline{C} \:D...

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edited Nov 27, 2022

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GATE ECE 2018 | Question: 47
The logic gates shown in the digital circuit below use strong pull-down $\text{nMOS}$ transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes ... values of $X_{3}X_{2}X_{1}X_{0}$ (out of the $16$ possible values) that give $Y=1$ is ________.

The logic gates shown in the digital circuit below use strong pull-down $\text{nMOS}$ transistors for LOW logic level at the outputs. When the pull-downs are off, high-va...

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recategorized Nov 27, 2022

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GATE ECE 2017 Set 2 | Question: 44
Figure Ⅰ shows a $4$-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are $20$ ns, $15$ ns and $10$ ns, respectively. Assume ... $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The output of the ripple carry adder will be stable at $t$ (in ns) = ___________

Figure Ⅰ shows a $4$-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and ...

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edited Nov 27, 2022

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GATE ECE 2017 Set 2 | Question: 16
Consider the circuit shown in the figure. The Boolean expression $F$ implemented by the circuit is $\overline{X} \overline{Y} \overline{Z} + X Y +\overline{Y} Z $ $\overline{X} Y \overline{Z} + X Z + \overline{Y} Z $ $\overline{X} Y \overline{Z} +XY + \overline{Y} Z $ $\overline{X} \overline{Y} \overline{Z} + XZ+ \overline{Y}Z $

Consider the circuit shown in the figure. The Boolean expression $F$ implemented by the circuit is$\overline{X} \overline{Y} \overline{Z} + X Y +\overline{Y} Z $$\overlin...

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edited Nov 27, 2022

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GATE ECE 2017 Set 2 | Question: 15
For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is XNOR XOR NOR OR

For the circuit shown in the figure, P and Q are the inputs and Y is the output.The logic implemented by the circuit isXNOR XORNOROR

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recategorized Nov 27, 2022

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GATE ECE 2016 Set 3 | Question: 45
For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a $\text{mod}-5\:\text{counter}$ $\text{mod}-6\:\text{counter}$ $\text{mod}-7\:\text{counter}$ $\text{mod}-8\:\text{counter}$

For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$...

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recategorized Nov 27, 2022

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GATE ECE 2016 Set 3 | Question: 44
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2$ ns, $1.5$ ns and $1$ ns, respectively. If all the inputs $P, Q, R, S$ and $T$ are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is _________

For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2$ ns, $1.5$ ns and $1$ ns, respectively. If all the inputs $P, Q, R, S$ and...

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recategorized Nov 27, 2022

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GATE ECE 2016 Set 3 | Question: 17
The logic functionality realized by the circuit shown below is $OR$ $XOR$ $NAND$ $AND$

The logic functionality realized by the circuit shown below is $OR$$XOR$$NAND$$AND$

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recategorized Nov 27, 2022

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GATE ECE 2015 Set 3 | Question: 38
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing NOR gates to NAND gates inverters to buffers NOR gates to NAND gates and inverters to buffers $5\: V$ to ground

An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the cir...

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recategorized Nov 27, 2022

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GATE ECE 2015 Set 3 | Question: 15
In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for logic $‘1’$. What logic gate does the circuit represent? $3$-input OR gate $3$-input NOR gate $3$-input AND gate $3$-input XOR gate

In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for...

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recategorized Nov 27, 2022

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GATE ECE 2014 Set 1 | Question: 16
Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of $1\: MHz$ are applied as shown. The frequency $(\text{in}\:kHz)$ of the waveform at $Q3$ is ________.

Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of $1\: MHz$ are applied as shown. The frequency $(\text{in}\:kHz)$ of th...

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recategorized Nov 27, 2022

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GATE ECE 2018 | Question: 46
In the circuit shown below, a positive edge-triggered $D$ Flip-Flop is used for sampling input data $D_{in}$ using clock $CK$. The XOR gate output $3.3$ volts for logic HIGH and $0$ volts for logic LOW levels. The data bit and clock periods are ... period is $0.3$, the average value (in volts, accurate to two decimal places) of the voltage at node $X$, is _________.

In the circuit shown below, a positive edge-triggered $D$ Flip-Flop is used for sampling input data $D_{in}$ using clock $CK$. The XOR gate output $3.3$ volts for logic H...

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recategorized Nov 21, 2022

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GATE ECE 2017 Set 1 | Question: 46
A finite state machine (FSM) is implemented using the D flip-flop A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are $Q_{A}Q_{B}=00,01,10$ and $11$. Assume that $X_{IN}$ is held at a constant logic ... states if $X_{IN}=0$ only two or four possible states if $X_{IN}=1$ only two or four possible states if $X_{IN}=0$

A finite state machine (FSM) is implemented using the D flip-flop A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are $Q_{A}Q_...

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recategorized Nov 21, 2022

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GATE ECE 2014 Set 3 | Question: 15
The circuit shown in the figure is a Toggle Flip Flop JK Flip Flop SR Latch Master-Slave D Flip Flop

The circuit shown in the figure is a Toggle Flip FlopJK Flip FlopSR LatchMaster-Slave D Flip Flop

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recategorized Nov 21, 2022

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GATE ECE 2014 Set 2 | Question: 41
The outputs of the two flip-flops $Q1$, $Q2$ in the figure shown are initialized to $0,0$. The sequence generated at $Q1$ upon application of clock signal is $01110 \dots$ $01010\dots$ $00110\dots$ $01100\dots$

The outputs of the two flip-flops $Q1$, $Q2$ in the figure shown are initialized to $0,0$. The sequence generated at $Q1$ upon application of clock signal is $01110 \dots...

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recategorized Nov 21, 2022

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GATE ECE 2016 Set 2 | Question: 17
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flip-flops $D_{1} \:, D_{2} \:, D_{3} \:, D_{4}$ and $D_{5}$ are initialized with ... $0$, respectively. The clocks has a $30\%$ duty cycle. The average power dissipated (in $mW$) in the resistor $R$ is _________

Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flip-flops $D_{1} \:, ...

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recategorized Nov 21, 2022

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GATE ECE 2015 Set 1 | Question: 42
In the circuit shown, $I_1=80$ mA and $I_2=4$ mA. Transistors $T_1$ and $T_2$ are identical. Assume that the thermal voltage $V_T$ is $26$ mV at $27^{\circ}C$. At $50^{\circ}C$, the value of the voltage $V_{12}=V_1 - V_2$ (in mV) is _______.

In the circuit shown, $I_1=80$ mA and $I_2=4$ mA. Transistors $T_1$ and $T_2$ are identical. Assume that the thermal voltage $V_T$ is $26$ mV at $27^{\circ}C$. At $50^{\c...

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recategorized Nov 21, 2022

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GATE ECE 2015 Set 1 | Question: 24
Consider a straight, infinitely long, current carrying conductor lying on the z-axis. Which one of the following plots (in linear scale) qualitatively represents the dependence of $H_{\phi}$ on $r$, where $H_{\phi}$ is the magnitude of the azimuthal component of magnetic field outside the conductor and $r$ is the radial distance from the conductor?

Consider a straight, infinitely long, current carrying conductor lying on the z-axis. Which one of the following plots (in linear scale) qualitatively represents the depe...

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recategorized Nov 21, 2022

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GATE ECE 2014 Set 3 | Question: 54
A region shown below contains a perfect conducting half-space and air. The surface current $\overrightarrow{K_{s}}$ on the surface of the perfect conductor is $\overrightarrow{K_{s}}= \hat{x}2$ amperes per meter. The tangential $\overrightarrow{H}$ field in the ... per meter $\hat{x}2$ amperes per meter $-\hat{z}2$ amperes per meter $\hat{z}2$ amperes per meter

A region shown below contains a perfect conducting half-space and air. The surface current $\overrightarrow{K_{s}}$ on the surface of the perfect conductor is $\overright...

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recategorized Nov 21, 2022

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GATE ECE 2014 Set 3 | Question: 41
In the circuit shown, $W$ and $Y$ are MSBs of the control inputs. The output $F$ is given by $F= W\overline{X}+\overline{W}X+\overline{Y}\overline{Z}$ $F= W\overline{X}+\overline{W}X+\overline{Y}Z$ $F= W\overline{X}\overline{Y}+\overline{W}X\overline{Y}$ $F= ( \overline{W}+\overline{X} )\overline{Y}\overline{Z}$

In the circuit shown, $W$ and $Y$ are MSBs of the control inputs. The output $F$ is given by$F= W\overline{X}+\overline{W}X+\overline{Y}\overline{Z}$$F= W\overline{X}+\ov...

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recategorized Nov 21, 2022

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GATE ECE 2012 | Question: 43
The state transition diagram for the logic circuit shown is

The state transition diagram for the logic circuit shown is

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recategorized Nov 21, 2022

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GATE ECE 2015 Set 2 | Question: 37
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod-$2$ counter mod-$4$ counter mod-$5$ counter mod-$6$ counter

The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod-$2$ counter mod-$4$ counter mod-$5$ counter mod-...

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recategorized Nov 21, 2022

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GATE ECE 2015 Set 2 | Question: 16
A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.

A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.

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recategorized Nov 21, 2022

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GATE ECE 2018 | Question: 31
A four-variable Boolean function is realized using $4\times 1$ multiplexers as shown in the figure. The minimized expression for $\text{F(U,V,W,X)}$ is $\left ( UV+\overline{U}\:\overline{V}\right )\overline{W}$ ... $\left ( U\:\overline{V}+\overline{U}\:V\right )\left (\overline{W}\: \overline{X}+\overline{W}\:X\right )$

A four-variable Boolean function is realized using $4\times 1$ multiplexers as shown in the figure.The minimized expression for $\text{F(U,V,W,X)}$ is $\left ( UV+\overli...

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recategorized Nov 21, 2022

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GATE ECE 2014 Set 1 | Question: 40
The output $F$ in the digital logic circuit shown in the figure is $F = \overline{X}\:Y\:Z + X\:\overline{Y}\:Z$ $F = \overline{X}\:Y\:\overline{Z} + X\:\overline{Y}\:\overline{Z}$ $F = \overline{X}\:\overline{Y}\:Z + X\:Y\:Z$ $F = \overline{X}\:\overline{Y}\:\overline{Z} + X\:Y\:Z$

The output $F$ in the digital logic circuit shown in the figure is$F = \overline{X}\:Y\:Z + X\:\overline{Y}\:Z$$F = \overline{X}\:Y\:\overline{Z} + X\:\overline{Y}\:\over...

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edited Sep 13, 2022

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GATE ECE 2014 Set 3 | Question: 16
Consider the multiplexer based logic circuit shown in the figure. Which one of the following Boolean functions is realized by the circuit? $F= W \overline{S_1} \: \overline{S_2}$ $F= WS_1+WS_2 + S_{1}S_{2}$ $F= \overline{W}+S_{1}+S_{2}$ $F= W\oplus S_{1}\oplus S_{2}$

Consider the multiplexer based logic circuit shown in the figure.Which one of the following Boolean functions is realized by the circuit?$F= W \overline{S_1} \: \overline...

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edited Sep 13, 2022

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GATE ECE 2016 Set 2 | Question: 43
In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source $V_{in}$ ... maximum sampling rate? $1$ megasamples per second $6$ megasamples per second $64$ megasamples per second $256$ megasamples per second

In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digita...

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recategorized Sep 12, 2022

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GATE ECE 2022 | Question: 54
Consider a real valued source whose samples are independent and identically distributed random variables with the probability density function, $f(x),$ as shown in the figure. Consider a $1$ bit quantizer that maps positive samples to value $\alpha$ and others to ... error, then $(\alpha^{\ast} - \beta^{\ast}) = $____________ (rounded off to two decimal places).

Consider a real valued source whose samples are independent and identically distributed random variables with the probability density function, $f(x),$ as shown in the fi...

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edited Sep 12, 2022

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GATE ECE 2022 | Question: 38
A state transition diagram with states $A, B,$ and $C,$ and transition probabilities $p_{1}, p_{2}, \dots, p_{7}$ is shown in the figure (e.g., $\text{p}_{1}$ denotes the probability of transition from state $A$ to $B$). For this state diagram, select the statement(s) which is/are ... $p_{1} + p_{4} + p_{7} = 1$ $p_{2} + p_{5} + p_{7} = 1$

A state transition diagram with states $A, B,$ and $C,$ and transition probabilities $p_{1}, p_{2}, \dots, p_{7}$ is shown in the figure (e.g., $\text{p}_{1}$ denotes the...

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edited Sep 12, 2022

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GATE ECE 2022 | Question: 41
Consider an $\text{FM}$ broadcast that employs the pre-emphasis filter with frequency response $H_{pe}(\omega) = 1 + \frac{j \omega}{\omega_{0}},$ where $\omega_{0} = 10^{4} \; \text{rad/sec}.$ For the network shown in the figure to act as a corresponding de-emphasis filter, the appropriate ... $R = 1 \; k \Omega, C = 2 \; \mu F$ $R = 2 \; k \Omega, C = 0.5 \; \mu F$

Consider an $\text{FM}$ broadcast that employs the pre-emphasis filter with frequency response$$H_{pe}(\omega) = 1 + \frac{j \omega}{\omega_{0}},$$where $\omega_{0} = 10^...

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edited Sep 12, 2022

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GATE ECE 2022 | Question: 36
The outputs of four systems $(S_{1}, S_{2}, S_{3},$ and $\text{S}_{4})$ corresponding to the input signal $\sin(t),$ for all time $t,$ are shown in the figure. Based on the given information, which of the four systems is/are definitely $\text{NOT LTI}$ (linear and time-invariant)? $S_{1}$ $S_{2}$ $S_{3}$ $S_{4}$

The outputs of four systems $(S_{1}, S_{2}, S_{3},$ and $\text{S}_{4})$ corresponding to the input signal $\sin(t),$ for all time $t,$ are shown in the figure.Based on th...

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edited Sep 12, 2022

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GATE ECE 2022 | Question: 24
An ideal $\text{MOS}$ capacitor (p-type semiconductor) is shown in the figure. The $\text{MOS}$ capacitor is under strong inversion with $V_{G} = 2 \; \text{V}.$ The corresponding inversion charge density $(Q_{IN})$ is $2.2 \; \mu \text{C /cm}^{2}.$ ... $Q_{IN}$ is ______________ $\mu \text{C/cm}^{2}$ (rounded off to one decimal place).

An ideal $\text{MOS}$ capacitor (p-type semiconductor) is shown in the figure. The $\text{MOS}$ capacitor is under strong inversion with $V_{G} = 2 \; \text{V}.$ The corr...

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edited Sep 12, 2022

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GATE ECE 2022 | Question: 21
The bar graph shows the frequency of the number of wickets taken in a match by a bowler in her career. For example, in $17$ of her matches, the bowler has taken $5$ wickets each. The median number of wickets taken by the bowler in a match is _______________ (rounded off to one decimal place).

The bar graph shows the frequency of the number of wickets taken in a match by a bowler in her career. For example, in $17$ of her matches, the bowler has taken $5$ wicke...

710 views

recategorized Sep 12, 2022